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TDA4AEN-Q1: eval board ddr route spacing

bob moss
Prodigy 90 points
Part Number: TDA4AEN-Q1

Tool/software:

the route spacing specified on the eval board are all 5mil and below.  that's really aggressive and not a practical number for high volume boards.  is it ok to use neck-down on the ddr signals to get them routed out from the bga field?  

  • 0
    TI__Guru 52125 points

    I'm not 100% clear on the question.  You mention 'route spacing is specified at 5mil' but then ask about necking down traces in BGA field or are you asking about neck down the route spacing in BGA areas?

    Regardless - there is no simple yes or no answer.  Overall timing margin is impacted by both signal integrity (trace neck-down) and signal coupling (space neck-down).  Simulation should help identify which is best approach for your PCB implementation.  Another option might be to change the trace impedance.  TI's EVM uses 40-ohm traces (wider) but 50-ohms traces might be another option (more narrow).  Note you might need to use different termination settings as you are adjusting the trace impedances.  Again - this is why we recommend simulations for customers to find the optimal solution/termination settings for there design.  (Link to LPDDR4 Design Guide)