This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

bootloader PLL workaround doubt

Other Parts Discussed in Thread: TMS320C6678

 

 

Hi all,

I am using Shannon EVM c6678 , MCSDK 2_00_00_11 , and  pdk_C6678_1_0_0_11.

I have the following doubt with respect to the bootloader.

In the TMS320C6678 silicon Errata it is mentioned that for boot modes other than i2c and spi,

the bootloader should perform PLL workaround for stable working.

ie It should jump back to the ROM loader  after performing PLL workaround

I believe the transfer to ROM loader  is done by the following code in c6xx_init.c

        exit = (void(*)())BOOT_ROM_ENTER_ADDRESS;

        (*exit)();

 

But for PCIe boot the iblPcieworkaround() function
initializes the PCIe and jumps to the start addresses directly Without  jumping back to ROM loader

Why is this so ?

Will it cause any stability issues ?

Also when I changed the bootloader code to jump to ROM loader  , It doesn’t boot (PCIe mode)

What is the issue ?

  • Shrish,

    The way the PLL work around is implemented in IBL is as below.

    1. During Power up, Irrespective of the boot mode dip swich settings on the EVM, the FPGA puts the i2c boot from 0x51 mode in the DEVSTAT register.

    2. So, the RBL jumps to i2c 0x51 address.

    3. IBL does the PLL work around

    4. The IBL then, reads back the boot mode dip switch values and updates the DEVSTAT register to what ever is set by the user and then jumps back to RBL (Please note that if the boot mode dip switch settings are really intended for i2c boot with 0x51 address, then the jump back to RBL does not happen).

    5. Now, the PLL work around is done in IBL, the RBL proceeds to the desired boot mode since the DEVSTAT register is updated with the user intended mode.

     

    -Aravind

  • hi aravind,

    The information you have given is correct

    but i think you have not got my doubt .

     

    In PCIe boot (non i2c) the bootloader is expected to jump back to ROM bootloader after executing the code

    "

          exit = (void (*)())BOOT_ROM_ENTER_ADDRESS;
          (*exit)();

    but after executing the IblPcieworkaround() function the bootloader jumps to the start address of the image directly and does go through the above code.

    Why is this ? Isn't it expected to jump to ROM bootloader ?

  • Shrish,

    In the PCIE boot mode, after IBL was executed for the PLL erreta, it will not jump back to RBL.  Becasue in the RBL, there is some code to intialize the PCIE registers, it is configured not to support Spread Spectrum Clocking, this causes trouble if the PCIE RC is a Personal Computer, which often uses SS clock.  

    Rather, in PCIE boot, the PCIE workaround code will configure the PCIE registers mainly for using SS clock, change DEVSTAT to PCIE boot and the code will stay inside IBL and continuosuly monitors the MAGIC address (0x87fffc for Shannon) to jump out.

    Regards, Eric