TDA4VH-Q1: PCIE_DAT2 address

Hi JPH,

I am not finding info either. Let me check internally on this.

Regards,

Takuma

Hi Takuma,

Did you get information on this subject ?

Thanks,

JPH

Hi JPH, 

No info for PCIE_DAT2. Looked through our older revision TRMs and TRM of older devices that reuse the same IPs. For everything I looked through, PCIE_DAT2 is only mentioned in the single paragraph that you have found.

Software driver only defines DAT0 and DAT1 spaces as well.

Regards,

Takuma

Hi JPH,

So, I got some info from the broader team. PCIE_DAT2 is mainly for address translation bypass, so there is no specific address for this region. It is the 2^48 Byte window in the 48-bit local address space, where translation between device address and PCIe address does not occur. This is the reason why there is no memory region similar to DAT0 and DAT1 space listed in excel sheet.

Regards,

Takuma

Hi Takuma,

Thanks for this information.

I understand that when the DMA’s CASEL (or ASEL?) field is set,  I can use any 48-bit address to access the slave PCIe controller. Did I get that right?

If so, that would mean that if my PCIe fabric uses 64-bit addressing, I would only be able to address endpoints whose 16 most significant address bits are 0. Is that correct?

Thanks,

JPH

Hi JPH,

Non-zero ASEL value will result in outbound ATU bypass. This is useful when the PCIe Controller is acting as an Endpoint and needs to read from or write to the remote Root-Complex's memory. Without outbound ATU bypass, the outbound ATU has to be setup to translate local (EP) address read/write transactions to PCIe Bus address transactions targeting the remote Root-Complex's memory. With ATU bypass, the local address can be identical to the remote Root-Complex's memory itself except for the ASEL bit which will be removed before the address is sent out over the PCIe link without translation - Bits 0 to 47 of the local address will be used as the read/write transaction address on the PCIe link as well.

PCIen_DAT0 => 128 MB window in the 32-bit Local Address Space => Translated by ATU to generate an address targeting a buffer in the PCIe Root-Complex's memory
PCIen_DAT1 => 4 GB window in the 64-bit Local Address Space => Translated by ATU to generate an address targeting a buffer in the PCIe Root-Complex's memory
PCIen_DAT2=> 2^48 Byte window in the 48-bit Local Address Space => Untranslated address identical to the buffer address in PCIe Root-Complex's memory

Regards,

Takuma

Hi Takuma,

Thanks for the clarification.

I just need extra information about the ASEL bit: reading your sentence, it seems that ASEL bit is in the same word as the  destination address, and that it will be removed by the hardware.

Does the user has to set this bit in the address word ? At which position? I didn't read such information anywhere.

Thank,

JPH

Hi Takuma,

Thanks again, your answer is very interesting, I did'nt get this information.

Is there a document where the ASEL subject is detailled ? 

If you have an example of non zero ASEL on C7x, I am interested.

Thanks,

JPH

Hi JPH,

My understanding for ASEL is that it is only relevant for cache coherency on the A53 cores for the AM67, AM64, AM62P, and maybe other Sitara family devices that do not have a MSMC memory in front of the A-core clusters so that data can be routed to ACP for cache coherence, and also relevant for PCIe for address translation bypass. Example I shared in my previous response is for J722S (AM67) and AM62P to show how ASEL can be set in devicetree. TDA4VH has a MSMC so it does not need to use ACP from ARM A core.

As such, we do not have any examples for C7x that uses non-zero ASEL.

Regards,

Takuma