Tool/software:
Hi all
We use sdk 10 with custom board.
During power cycling tests, a boot failure issue was identified - the system hangs at the Secondary Program Loader (SPL) phase without successfully initializing U-Boot.
Log:
[2025-08-13 20:41:08.451] U-Boot SPL 2024.04-ti-g46475e143ccd (Jul 23 2025 - 02:54:35 +0000)
[2025-08-13 20:41:08.491] SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
[2025-08-13 20:41:08.540] Trying to boot from SPI
[2025-08-13 20:41:08.554] Boot MCU1_0 from Partition B!
[2025-08-13 20:41:08.603] Authentication passed
[2025-08-13 20:41:08.603] Authentication passed
[2025-08-13 20:41:08.619] Authentication passed
[2025-08-13 20:41:08.646] Loading Environment from nowhere... OK
[2025-08-13 20:41:08.646] Authentication passed
[2025-08-13 20:41:08.646] Authentication passed
[2025-08-13 20:41:08.680] Starting ATF on ARM64 core...
[2025-08-13 20:41:08.680]
[2025-08-13 20:41:08.680] NOTICE: BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty
[2025-08-13 20:41:08.680] NOTICE: BL31: Built : 16:09:05, Feb 9 2024
[2025-08-13 20:41:08.695] I/TC:
[2025-08-13 20:41:08.696] I/TC: OP-TEE version: 4.2.0-dev (gcc version 13.3.0 (GCC)) #1 Fri Apr 12 09:51:21 UTC 2024 aarch64
[2025-08-13 20:41:08.773] I/TC: WARNING: This OP-TEE configuration might be insecure!
[2025-08-13 20:41:08.773] I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
[2025-08-13 20:41:08.773] I/TC: Primary CPU initializing
[2025-08-13 20:41:08.773] I/TC: GIC redistributor base address not provided
[2025-08-13 20:41:08.773] I/TC: Assuming default GIC group status and modifier
[2025-08-13 20:41:08.773] I/TC: SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
[2025-08-13 20:41:08.773] I/TC: HUK Initialized
[2025-08-13 20:41:08.773] I/TC: Activated SA2UL device
[2025-08-13 20:41:08.773] I/TC: Enabled firewalls for SA2UL TRNG device
[2025-08-13 20:41:08.773] I/TC: SA2UL TRNG initialized
[2025-08-13 20:41:08.773] I/TC: SA2UL Drivers initialized
[2025-08-13 20:41:08.773] I/TC: Primary CPU switching to normal world boot
[2025-08-13 20:41:08.917]
[2025-08-13 20:41:08.917] U-Boot SPL 2024.04-ti-gcf9543435d2b (Aug 07 2025 - 06:25:51 +0000)
[2025-08-13 20:41:08.917] SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
[2025-08-13 20:41:09.036] Detected: J7X-BASE-CPB rev E3
[2025-08-13 20:41:09.036] Detected: J7X-VSC8514-ETH rev E2
[2025-08-13 20:41:09.036] Trying to boot from SPI
[2025-08-13 20:41:09.036] k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:235
[2025-08-13 20:41:09.036] k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
[2025-08-13 20:41:09.036] jedec_spi_nor flash@0: non-uniform erase sector maps are not supported yet.
[2025-08-13 20:41:09.068] Authentication passed
[2025-08-13 20:41:09.084] Authentication passed
[2025-08-13 20:43:09.321]
[2025-08-13 20:43:09.321] U-Boot SPL 2024.04-ti-g46475e143ccd (Jul 23 2025 - 02:54:35 +0000)
Normal startup log：
[2025-08-13 20:43:09.321] U-Boot SPL 2024.04-ti-g46475e143ccd (Jul 23 2025 - 02:54:35 +0000)
[2025-08-13 20:43:09.380] SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
[2025-08-13 20:43:09.428] Trying to boot from SPI
[2025-08-13 20:43:09.444] Boot MCU1_0 from Partition B!
[2025-08-13 20:43:09.492] Authentication passed
[2025-08-13 20:43:09.492] Authentication passed
[2025-08-13 20:43:09.508] Authentication passed
[2025-08-13 20:43:09.536] Loading Environment from nowhere... OK
[2025-08-13 20:43:09.536] Authentication passed
[2025-08-13 20:43:09.536] Authentication passed
[2025-08-13 20:43:09.569] Starting ATF on ARM64 core...
[2025-08-13 20:43:09.569]
[2025-08-13 20:43:09.569] NOTICE: BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty
[2025-08-13 20:43:09.569] NOTICE: BL31: Built : 16:09:05, Feb 9 2024
[2025-08-13 20:43:09.585] I/TC:
[2025-08-13 20:43:09.585] I/TC: OP-TEE version: 4.2.0-dev (gcc version 13.3.0 (GCC)) #1 Fri Apr 12 09:51:21 UTC 2024 aarch64
[2025-08-13 20:43:09.659] I/TC: WARNING: This OP-TEE configuration might be insecure!
[2025-08-13 20:43:09.659] I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
[2025-08-13 20:43:09.659] I/TC: Primary CPU initializing
[2025-08-13 20:43:09.659] I/TC: GIC redistributor base address not provided
[2025-08-13 20:43:09.659] I/TC: Assuming default GIC group status and modifier
[2025-08-13 20:43:09.659] I/TC: SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
[2025-08-13 20:43:09.659] I/TC: HUK Initialized
[2025-08-13 20:43:09.659] I/TC: Activated SA2UL device
[2025-08-13 20:43:09.659] I/TC: Enabled firewalls for SA2UL TRNG device
[2025-08-13 20:43:09.659] I/TC: SA2UL TRNG initialized
[2025-08-13 20:43:09.659] I/TC: SA2UL Drivers initialized
[2025-08-13 20:43:09.659] I/TC: Primary CPU switching to normal world boot
[2025-08-13 20:43:09.812]
[2025-08-13 20:43:09.812] U-Boot SPL 2024.04-ti-gcf9543435d2b (Aug 07 2025 - 06:25:51 +0000)
[2025-08-13 20:43:09.812] SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
[2025-08-13 20:43:09.926] Detected: J7X-BASE-CPB rev E3
[2025-08-13 20:43:09.926] Detected: J7X-VSC8514-ETH rev E2
[2025-08-13 20:43:09.926] Trying to boot from SPI
[2025-08-13 20:43:09.926] k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:235
[2025-08-13 20:43:09.926] k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
[2025-08-13 20:43:09.926] jedec_spi_nor flash@0: non-uniform erase sector maps are not supported yet.
[2025-08-13 20:43:09.959] Authentication passed
[2025-08-13 20:43:09.974] Authentication passed
[2025-08-13 20:43:10.968]
[2025-08-13 20:43:10.968]
[2025-08-13 20:43:10.968] U-Boot 2024.04-ti-gcf9543435d2b (Aug 07 2025 - 06:25:51 +0000)
[2025-08-13 20:43:10.968]
[2025-08-13 20:43:10.968] SoC: J721E SR2.0 HS-FS
[2025-08-13 20:43:10.968] Model: Texas Instruments J721e EVM
[2025-08-13 20:43:10.968] Board: J721EX-PM2-SOM rev E8
[2025-08-13 20:43:10.968] DRAM: 2 GiB (effective 4 GiB)
[2025-08-13 20:43:11.523] Core: 115 devices, 34 uclasses, devicetree: separate
[2025-08-13 20:43:11.523] Flash: 0 Bytes
[2025-08-13 20:43:11.523] MMC: mmc@4f80000: 0, mmc@4fb0000: 1
[2025-08-13 20:43:11.523] Loading Environment from nowhere... OK
[2025-08-13 20:43:11.523] In: serial@2800000
[2025-08-13 20:43:11.523] Out: serial@2800000
[2025-08-13 20:43:11.523] Err: serial@2800000
[2025-08-13 20:43:11.523] am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA00101 cpsw_ver: 0x6BA80100 ale_ver: 0x00293904 Ports:1
[2025-08-13 20:43:11.523] Detected: J7X-BASE-CPB rev E3
[2025-08-13 20:43:11.523] Detected: J7X-VSC8514-ETH rev E2
[2025-08-13 20:43:11.523] Net: PHY PassiveMode: 0x0000
[2025-08-13 20:43:11.619] eth0: ethernet@46000000port@1
[2025-08-13 20:43:11.667] k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:235
[2025-08-13 20:43:11.667] k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
[2025-08-13 20:43:11.667] jedec_spi_nor flash@0: non-uniform erase sector maps are not supported yet.
[2025-08-13 20:43:12.002] SF: Detected s28hs512t with page size 256 Bytes, erase size 256 KiB, total 64 MiB
[2025-08-13 20:43:12.044] device 0 offset 0x680000, size 0x9
[2025-08-13 20:43:12.044] SF: 9 bytes @ 0x680000 Read: OK
[2025-08-13 20:43:12.044] The current system is on Partition B, set bootpart 0:2.
[2025-08-13 20:43:12.044] device 0 offset 0x3f80000, size 0x40000
[2025-08-13 20:43:12.044] SF: 262144 bytes @ 0x3f80000 Read: OK
[2025-08-13 20:43:12.044] Hit any key to stop autoboot: 2 1 0
[2025-08-13 20:43:14.199] Device at ufs@4e84000 up at:cdns-ufs-pltfm ufs@4e84000: [RX, TX]: gear=[3, 3], lane[2, 2], pwr[FAST MODE, FAST MODE], rate = 2
[2025-08-13 20:43:14.224] scanning bus for devices...
In addition to this problem, I still have some technical concerns:
The numbered items (1, 2, 3) marked in red indicate which phases of the boot sequence respectively?
BR
liupt
