DM8148 DMM's interleave

jun yang62451

Dear sir!

I have some confusion on DM8148's DMM and need your help.

In sprugz8-Digital Media Processors Technical Reference Manual.pdf,there are following descriptions:
P835, 5.1.2 Features ： Ability to interleave the DDR data between two EMIF banks, using the programmable multi-zone DRAM memory mapping.
This increases the memory throughput by a factor of 2. Up-to four unique memory sections supported.
P841, 5.2.1.6 Section Mapping ： For optimal system performance, it is recommended to enable interleaving between the 2 EMIF banks and thus have same sized memory on both the EMIF banks.

In my system, I want to use two 16bit DDR3 phys. I have 2 solutions as following:
       Solution1: Connect one 16bit DDR3 phy to DM8148's DDR3[0] and leave DDR3[0]'s other 16bit; the same, connect one 16bit DDR3 phy to DM8148's DDR3[1] and leave DDR3[1]'s other 16bit.
      Solution 2: Connect two 16bit DDR3 phys to DM8148's DDR3[0] and disable DDR3[1].
       Depend on DMM's interleave features descript on the above spec, is the data throughput on solution 1 twice than it on solution 2? which solution is better?

Thanks.

over 13 years ago

0 Ish Kumar Dham over 13 years ago

TI__Prodigy 100 points

The double performance when using interleaving comes when using one memory of 32 bit width vs using two 32 bit width memories using interleaving at the same frequency.

When using two 16 bit memories (Solution 1) vs one 32 bit memory (Solution 2) roughly the same performance would be observed. There may be some variation in performance because of larger effective pages that might be possible with solution 1. This would depend some on the application.

I would recomend making the choice based on what is easier for your board design - as the overall performance may be similar. There would of course be some differences based off the application. Solution 1 may show some gains for most applications - because it allows for more pages to be open and more commands to be outstanding concurrently. But the differences is definitely not double.

0 jun yang62451 over 13 years ago in reply to Ish Kumar Dham

Intellectual 390 points

Sorry I couldn’t understand the meaning of “The double performance when using interleaving comes when using one memory of 32 bit width vs using two 32 bit width memories using interleaving at the same frequency”, do you mean that I have to using interleaving to double the performance?

My comprehension is that, all without using interleaving, two 32bit width memories have double performance than one 32bit width memory, because the data width of two 32bit width memories were double. Is that correct?

Moreover, would you provide detailed information of the interleave function?

Thanks.

0 jun yang62451 over 13 years ago in reply to Ish Kumar Dham

Intellectual 390 points

Dear Kumar Dham.

Moreover, would you provide detailed information of the interleave function?

Thanks

0 Ish Kumar Dham over 13 years ago in reply to jun yang62451

TI__Prodigy 100 points

I think the double performance note may be a little confusing.

Lets say 32 bit interface at clock rate frequency F, gives some performance X

Two 32 bit interfaces at the same clock rate, could give performace 2X in both the conditions - interleave and non-interleave.

In the non-interleave the memory map may look something like:

0x8000_0000 - 0xbfff_ffff : DDR0
0xc000_0000 - 0xffff_ffff : DDR1

In this case the responsibility of balancing the load across the two DDRs is upto software. How ever even with a good allocation - it may happen that there are periods of imbalance. This may impact the net performance that can be reliably realized.

In the interleaved mode the memory map may look like:

0x8000_0000 - 0xffff_ffff : Interleaved on DDR0, DDR1

This provides a single memory map that is split at interleave granularity across the two interfaces. This may provide an even loading ,more easily and hence the expected scale in performance may be realized.

Interleaving can be 128 byte, 256 byte or 512 byte. So if it is 128 bytes the memory map would really look like:

128 bytes - DDR0
128 bytes - DDR1
128 bytes - DDR0
128 bytes - DDR1
...

The interleaving can be programmed using LISA_MAP registers of DMM.

Interleaving is not helping in any magical form. It just makes it easier to balance the two interfaces.

In your question, 2 16 bit vs 1 32 bit - having a single memory interface may provide the same balancing. In such cases there may not be gross performance differences. How ever there may be subtle differences that play out based off how the page opening / closing etc works out.

Hope this helps.

Regards

Ish

0 jun yang62451 over 13 years ago in reply to Ish Kumar Dham

Intellectual 390 points

Dear Ish Kumar Dham.

Thanks for your definite reply. I know.

0 Omin Chou over 13 years ago in reply to jun yang62451

Genius 3555 points

Dear Ish,

I use the solution 1(Connect one 16bit DDR3 phy to DM8148's DDR3[0] and leave DDR3[0]'s other 16bit; the same, connect one 16bit DDR3 phy to DM8148's DDR3[1] and leave DDR3[1]'s other 16bit.) to implement my board. Unfortunately, I modify GEL setting to match the current DDR design that the result will bring about the unstable status. Please see my modification as below. I use two 128MB 16bit DDR3 on each bank. Can you indicate where I do not modify yet? Thanks a lot.

1. DDR3 parameters

=======================================================

#define DDR3_EMIF_SDRAM_CONFIG_DEFINE 0x61837AB2 // change to 16bit data bus width

=======================================================

2. EMIF/DDR FUNCTIONS

=======================================================

/*Program the DMM to Access EMIF0 and EMIF1*/
   WR_MEM_32(DMM_LISA_MAP__0, 0x0);
   WR_MEM_32(DMM_LISA_MAP__1, 0x0);
   WR_MEM_32(DMM_LISA_MAP__2, 0x80440300);
   WR_MEM_32(DMM_LISA_MAP__3, 0xC0440300);

   GEL_TextOut("\tBusy reading back DMM registers Please wait ...\n","Output",1,1,1);
   while(RD_MEM_32(DMM_LISA_MAP__0)!=0x0);
   while(RD_MEM_32(DMM_LISA_MAP__1)!=0x0);
   while(RD_MEM_32(DMM_LISA_MAP__2)!=0x80440300);
   while(RD_MEM_32(DMM_LISA_MAP__3)!=0xC0440300);
   GEL_TextOut("\tDMM register read successfully \n","Output",1,1,1);

=======================================================

B.R.

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DM8148 DMM's interleave