TDA4VH-Q1: TDA4VH RTOS0902 SGMII7,8 SERDES4

Tool/software:

Hi,

TDA4VH RTOS0902 SGMII7,8 SERDES4,
My code :

static Board_STATUS autox_Board_CfgSgmii_serdes4_sgmii78(void)
{
    CSL_SerdesResult result;
    CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
    CSL_SerdesLaneEnableParams serdesLaneEnableParams  = {0};
    uint32_t laneNum,laneNum2;
    uint32_t laneMask;

    laneNum  = 2; 
    laneNum2 = 3;
    laneMask = 0xC;

    memset(&serdesLaneEnableParams, 0, sizeof(serdesLaneEnableParams));

    /* SGMII Config */
    serdesLaneEnableParams.serdesInstance    = (CSL_SerdesInstance)CSL_TORRENT_SERDES4;
    serdesLaneEnableParams.baseAddr          = CSL_WIZ16B8M4CT3_2_WIZ16B8M4CT3_BASE;
    serdesLaneEnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;
    serdesLaneEnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT0;
    serdesLaneEnableParams.linkRate          = CSL_SERDES_LINK_RATE_1p25G;
    serdesLaneEnableParams.numLanes          = 2U;
    serdesLaneEnableParams.laneMask          = laneMask;
    serdesLaneEnableParams.SSC_mode          = CSL_SERDES_NO_SSC;
    serdesLaneEnableParams.phyType           = CSL_SERDES_PHY_TYPE_SGMII;
    serdesLaneEnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;
    serdesLaneEnableParams.phyInstanceNum    = BOARD_SERDES_LANE_SELECT_CPSW;
    serdesLaneEnableParams.pcieGenType       = CSL_SERDES_PCIE_GEN3;

    serdesLaneEnableParams.laneCtrlRate[laneNum] = CSL_SERDES_LANE_FULL_RATE;
    serdesLaneEnableParams.loopbackMode[laneNum] = CSL_SERDES_LOOPBACK_DISABLED;

    serdesLaneEnableParams.laneCtrlRate[laneNum2] = CSL_SERDES_LANE_FULL_RATE;
    serdesLaneEnableParams.loopbackMode[laneNum2] = CSL_SERDES_LOOPBACK_DISABLED;
    CSL_serdesPorReset(serdesLaneEnableParams.baseAddr);

    /* Select the IP type, IP instance num, Serdes Lane Number */
    CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
                       serdesLaneEnableParams.phyType,
                       serdesLaneEnableParams.phyInstanceNum,
                       serdesLaneEnableParams.serdesInstance,
                       laneNum);
    CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
                       serdesLaneEnableParams.phyType,
                       serdesLaneEnableParams.phyInstanceNum,
                       serdesLaneEnableParams.serdesInstance,
                       laneNum2);

    result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
                                 serdesLaneEnableParams.baseAddr,
                                 serdesLaneEnableParams.refClock,
                                 serdesLaneEnableParams.refClkSrc,
                                 serdesLaneEnableParams.serdesInstance,
                                 serdesLaneEnableParams.phyType);

    if (CSL_SERDES_NO_ERR != result)
    {
        return BOARD_FAIL;
    }
    /* Assert PHY reset and disable all lanes */
    CSL_serdesDisablePllAndLanes(serdesLaneEnableParams.baseAddr,
                                 serdesLaneEnableParams.numLanes,
                                 serdesLaneEnableParams.laneMask);

    /* Load the Serdes Config File */
    result = CSL_serdesEthernetInit(&serdesLaneEnableParams);
    /* Return error if input params are invalid */
    if (CSL_SERDES_NO_ERR != result)
    {
        return BOARD_FAIL;
    }

    /* Common Lane Enable API for lane enable, pll enable etc */
    laneRetVal = CSL_serdesLaneEnable(&serdesLaneEnableParams);
    if (0U != laneRetVal)
    {
        return BOARD_FAIL;
    }

    return BOARD_SOK;
}

Got Err:

[MCU2_0]   1271.818325 s: EnetMcm: CPSW_9G on MAIN NAVSS
[MCU2_0]   1271.828215 s: EthFw_initLinkArgs into macPort=6 
[MCU2_0]   1271.828257 s: ZD: *EthFwBoard_findPortCfg 
[MCU2_0]   1271.828288 s: ZD: *EthFwBoard_findPortCfg chk port 0 6
[MCU2_0]   1271.828318 s: ZD: *EthFwBoard_findPortCfg chk port 1 6
[MCU2_0]   1271.828348 s: ZD: *EthFwBoard_findPortCfg chk port 3 6
[MCU2_0]   1271.828377 s: ZD: *EthFwBoard_findPortCfg chk port 4 6
[MCU2_0]   1271.828407 s: ZD: *EthFwBoard_findPortCfg chk port 5 6
[MCU2_0]   1271.828437 s: ZD: *EthFwBoard_findPortCfg chk port 6 6
[MCU2_0]   1271.828476 s: EthFw_initLinkArgs into macPort=6 status  0
[MCU2_0]   1271.828508 s: EthFw_initLinkArgs done i=1 macPort=6 
[MCU2_0]   1271.828688 s: CpswMacPort_setSgmiiInterface: MAC 7: SERDES PLL is not locked
[MCU2_0]   1271.828722 s: : -9
[MCU2_0]   1271.828740 s: CpswMacPort_setSgmiiInterface: 
[MCU2_0]   1271.828760 s: : -1
[MCU2_0]   1271.828781 s: Assertion @ Line: 2332 in src/mod/cpsw_macport.c: BFALSE

how to configure the sgmii on port 7,8 SERDES4?

thanks.

Dongzhang