AM3517 - GPIO's specifications

Yuriy Ivanov said:

1. Please explain the requirement for input signals tT (tF and tR) specified in the processor manual in section 3.3 DC Electrical Characteristics table 3-4

Does it mean that signals with rise or fall edge worse then 10 ns should't be applied to GPIO?
If it right then signals with open drain not be directly conected to GPIO. Is't it?

This the input transition requirements across temperature and voltage to ensure adherence to the timing parameters.

Yuriy Ivanov said:

2. Please explain value of Ball Reset Release State of GPIO - PU and PD. 

Does it mean that after a reset these pins are configured as outputs with active levels Vol and Voh?

Look at the AM3517 datasheet in Section 2.2, entitled Ball Characteristics.  At the beginning of this section the various columns, including the Ball Reset Rel. State, are described with a decode of the Alpha-Numeric symbols.

For example, the PD state refers to the buffer drives Vol with an active pulldown resistor.

Yes, you are correct.  This parameter defines the maximum time allowed for an input signal to rise from 10% to 90% or fall from 90% to 10%.  I would like to add to Brandon's reply by saying these requirement s apply to all inputs unless otherwise specified in respective peripheral timing requirements sections of the data sheet.

This requirement also limits processor power consumption.  The static current consumption of an input buffer peaks to its maximum value when the input voltage is approximately 0.5 VDD because both p-channel and n-channel transistors or turned on at the same time.  To minimize this current you should minimize the time it takes for an input signal to transition.

You can connect open-drain or open-source signals as long as the impedance of the respective pull-up or pull-down can pull this signal to the non-active state within the maximum rise or fall time specified.

In similar processor data sheets, the Ball Reset Release State column of the Ball Characteristics Table normally contains one of the following seven values to indicate the state of the respective pin after reset is released.  

0 indicates the pin is driven low by the output buffer and the internal pull-down is turned off.

0(PD) indicates the pin is driven low by the output buffer and the internal pull-down is turned on.

1 indicates the pin is driven high by the output buffer and the internal pull-up is turned off.

1(PU) indicates the pin is driven high by the output buffer and the internal pull-up is turned on.

Z indicates the pin is in a high impedance state.

L indicates the pin is in a high impedance state and the internal pull-down is turned on.

H indicates the pin is in a high impedance state and the internal pull-up is turned on.

By comparing the comparing similar pin functions of this processor with other processors, it appears PD indicates the pin is in a high impedance state and the internal pull-down is turned on and PU indicates the pin is in a high impedance state and the internal pull-up is turned on.  I’m going to forward your forum post to a couple of people and ask them to confirm the meaning of PD and PU.

Regards,

Paul

Paul said:

0(PD) indicates the pin is driven low by the output buffer and the internal pull-down is turned on.

Paul said:

it appears PD indicates the pin is in a high impedance state and the internal pull-down is turned on

 But it's different states.
In the second case I can use these pins as inputs and in the first case I can not do it.

TABLE 2-1. Ball Characteristics indicates BALL RESET REL STATE [6] and RESET REL MODE [7].

For many pins RESET REL STATE [6] is PU (The buffer drives VOH) or PD (The buffer drives VOL).

Also for these pins RESET REL MODE [7] = 7 (safe_mode). In the safe_mode, the buffer is configured in high-impedance.

One statement contradicts the other.