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66AK2H06: The exception of MDMAERREVT XMC VBUSM error event

Part Number: 66AK2H06

Tool/software:

Hi,

1) Recently, an exception occurred in on-site devices. The relevant exception information is as follows. We have simulated various exception tests but failed to reproduce the same exception record information. The feature of exception is only Event 110. There is no other Event, for example memory protection exception caused by local access at xxxxxxxx.

Exception Information:
--- External exception happened. MEXPFLAG[3]=0x00004000

Event 110: MDMAERREVT XMC VBUSM error event
MDMA read status error detected XID (Transaction ID)= 15
Data error

Related register contents:
B3 = 0x10858A00 return pointer of caller
A4 = 0x23A80000 first input parameter of caller
B4 = 0x00005A5A second input parameter of caller
B14 = 0x0C20D9C8 data pointer
B15 = 0x10804060 stack pointer
NTSR = 0x0001820F NMI/Exception Task State Register
NRP = 0x10858690 Nonmaskable Interrupt Return Pointer Register
EFR = 0x40000000 Exception flag register
ITSR = 0x0000000D Interrupt task state register
IRP = 0x10866E80 Interrupt Return Pointer Register


2) What's the meaning of Transaction ID in MDMA Bus Error Register (MDMAERR)? The numerical range is 0~15. We does not find it in the manual.

XID/Transaction ID: Stores the transaction ID (RID or WID) when a read or write error is detected.


Regards,

GQ Zhou

  • Hi,

    Recently, an exception occurred in on-site devices. The relevant exception information is as follows. We have simulated various exception tests but failed to reproduce the same exception record information. The feature of exception is only Event 110.

    A similar problem is discussed in the below thread. Please do check whether it helps. 

    Previous E2E Post : https://e2e.ti.com/support/processors-group/processors/f/processors-forum/799521/tms320tci6618-vbusm-error-event-while-fetching-instructions-near-the-end-of-msm-region?

    Reference Document:  https://www.ti.com.cn/cn/lit/an/sprace2/sprace2.pdf?

    What's the meaning of Transaction ID in MDMA Bus Error Register (MDMAERR)? The numerical range is 0~15. We does not find it in the manual.

    XID/Transaction ID: Stores the transaction ID (RID or WID) when a read or write error is detected.

    The transaction ID, is just a tag used internally by the bus fabric, helps us infer which master caused the error.

    Regards,

    Betsy Varughese

  • Hi,

    Thank you for the reply!

    1)The post is not helpful and we have studied the manual(sprace2.pdf) repeatedly. Our question is why only Event 110. Usually it appears together with other Event.

    2)We still don't know the meaning of Transaction ID 0~15? Is it equivalent to Master ID in the manual(sprs866f.pdf)? The numerical range of Master ID is 0~255.


    Regards,

    GQ Zhou

  • Hi GQ Zhou,

    1)The post is not helpful and we have studied the manual(sprace2.pdf) repeatedly. Our question is why only Event 110. Usually it appears together with other Event.

    I think the issue is aligns with a system master -triggered exception, i.e, a transaction initiated by a non-cpu bus master.

    See , the C66x CorePac Guide :- https://www.ti.com/lit/ug/sprugw0c/sprugw0c.pdf

    We still don't know the meaning of Transaction ID 0~15? Is it equivalent to Master ID in the manual(sprs866f.pdf)? The numerical range of Master ID is 0~255.

    No, it's not. The transaction ID identifies which of the master's outstanding requests failed( i.e, It tells us which slot or out of up to 16 in-flight requests had the error).

    Regards,

    Betsy Varughese

  • Hi,

    Thank you for the reply!

    We need the detailed definition of Transaction ID for analyzing on-site issues. Could you please help us find it?
    We conducted simulated exception tests of Event 110. In the same experiment, Transaction ID behaves like a random number and this confuses us.

    Regards,

    GQ Zhou

  • Hi GQ Zhou,

    We conducted simulated exception tests of Event 110. In the same experiment, Transaction ID behaves like a random number and this confuses us.

    This is expected behavior. These IDs are assigned dynamically from a 0–15 range pool. The ID observed at any given time primarily depends on the pipeline timing and outstanding requests at the moment of the exception. Therefore, for the same experiment or code path, different IDs may appear across multiple runs.

    I was unable to find any detailed explanation in the existing documentation, aside from the note: "Stores the transaction ID (RID or WID) when a read or write error is detected."

    Regards,

    Betsy Varughese