Hello,
We want to connect our C6678 processor to an FPGA over PCIe link. DSP is assigned as RC and FPGA is assigned as EP.
FPGA is verified by means of a third-party tool called PCITree on a Personal Computer. Its configuration space can be retrieved normally
and PC BIOS assigns base addresses to its BARs correctly.
However, when we want to use our DSP as Root Complex, we are facing with some problems. The flow of our application goes as follows:
1. We follow the initialization procedures in the same way with PCIe sample project in the MCSDK.
2. We observe that link is up.
3. We read remote configuration registers for root complex as given the following code sniplet.(Which corresponds to the local PCIe configuration registers of FPGA)
// READ DEVICE ID & VENDOR ID
memset (&myRegs, 0, sizeof(myRegs));
memset (&myRemoteCfgDevAndVendorID, 0, sizeof(myRemoteCfgDevAndVendorID));
myRegs.vndDevId = &myRemoteCfgDevAndVendorID;
if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_REMOTE, &myRegs)) != pcie_RET_OK)
{
System_printf ("Read REMOTE DEVICE AND VENDOR ID register failed!\n");
}
// READ BAR REGISTERS
memset (&myRegs, 0, sizeof(myRegs));
memset (&myRemoteCfgBars, 0, sizeof(myRemoteCfgBars));
myRegs.type0BarIdx = &myRemoteCfgBars;
for(barNum=0; barNum < 6; barNum++)
{
myRemoteCfgBars.idx = barNum;
if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_REMOTE, &myRegs)) != pcie_RET_OK)
{
System_printf ("Read REMOTE BAR CONFIGURATION register failed!\n");
}
}
4. We can retrieve Device and Vendor IDs correctly. However, all BARs have the value of zero.
5. We also cannot write a desired value into any of BARs.
Why cannot we read the value of BARs although we can reach the configuration space of the EP???
Thanks in advance,
Hakan
