AM625: SK-AM625 : CSI2/DHY ADV7282 Confirmation regrading the data received at-least till DPhy

Hello,

Can you check this CSI debugging FAQ and see if you may have missed anything?

• [FAQ] Most common problems encountered when developing camera applications on the AM6x

Thanks,

Jianzhong Xu

Thanks for the response.

I have completed most of the above steps.

We are facing issues only with the ADV7282AM, are checking layer by layer.

To verify each layer, we made following changed to validate  DPHY and CSI behavior between  IMX219 and ADV7282Am in various configuration :

1. I2C: Shell script to configure I2C for various operating modes.

2. V4L2: Dummy CSI-based camera input driver without I2C.

3. CSI driver : logging all register setting and configuring link frequency
4. DPhy driver: logging all register setting
5. Changing number of data-lane enabled using DTB
6. Checking the following register dynamically 
   1. 0x30101048 (VBUS2APB_VBUSP_APB_CSI2RX_DPHY_STATUS Register)
   2. 0x30111000 
   3. 0x30101020 VBUS2APB_VBUSP_APB_CSI2RX_INFO_IRQS
   4. 

Based on the above, my observations are as follows:

1. If data is being received at the CSI layer (regardless of format), the register 0x30101048 shows values like 0x00222307 or 0x00223307 for lane status.

2. In the case of ADV7282AM, the D-PHY does not appear to receive any data.

3. With the IMX219, changing the link frequency impacts only the FPS (frames per second), without affecting other parameter

Any other info or steps for debugging the CSI-2 RX and MIPI D-PHY peripherals would be appreciated at this point 

A Karthik said:

With the IMX219, changing the link frequency impacts only the FPS (frames per second), without affecting other parameter

How about ADV7282AM? What data rate is the sensor operating at and what data rate did you configure the D-PHY to run?

Checked various link frequency 297000000, 456000000, 216000000(Clock  CSI pins as observed in oscilloscope  ) 

ADV7282AM Mode :  the video data is output in a progressive format at a nominal data rate of 432 Mbps (Ref:ADV7282AM datasheet )

My understanding AM625 does not support interlaced format as it does not have ISP

Any other info or steps for debugging the CSI-2 RX and MIPI D-PHY peripherals would be highly appreciated at this point 

A Karthik said:

the video data is output in a progressive format at a nominal data rate of 432 Mbps

Please make sure ADV7282AM output is in MIPI CSI format.

Jianzhong Xu said:

What data rate is the sensor operating at

Sorry, I meant the lane speed not the data rate. Lane speed is higher than the actual data rate due to protocol and blanking overhead.

You'll need to configure the D-PHY lane speed to match the lane speed of the sensor. For example, if sensor lane speed is 500Mbps, you'll need to set the link frequency to 250Mbps in sensor device tree overlay. D-PHY lane speed (bps) = 2 x link-frequency (Hz).

Yes, we am aware of it, that why we have use 297000000 as link frequency, ref (github.com/.../adv7282m-overlay.dts) base on raspberry pi also. Then also we are unable to read or observer any change in the register 

We checked ADV7282-m setup  with raspberry pi 3 b+ module(Linux version : Linux raspberrypi 6.12.25+rpt-rpi-v8). Its is working fine test pattern

 The driver use  the following configuration in for linux frequency

static const s64 adv7180_link_freqs[] = {
    [INTERLACED_IDX] = 108000000,
    [I2P_IDX] = 216000000, //progressive
};

we have tested with link-frequency  216000000 also 

Any other info or steps for debugging the CSI-2 RX and MIPI D-PHY peripherals would be appreciated at this point.

What's the content of bits [4:0] of register 0x30110B00 (PCS_TX_DIG_TBIT0)? This register contains the lane speed of the D-PHY.

Please find the register value below

Memory mapped at address 0xffff90271000.
Read at address  0x30110B00 (0xffff90271b00): 0x00000129

This value means [4:0] is 9, which means the lane speed is between 400Mbps and 480Mbps, according to the D-PHY driver: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/phy/cadence/cdns-dphy-rx.c?h=ti-linux-6.12.y#n71.

Is your sensor ADV7282-m running at this lane speed? If your sensor is running at 216Mbps, this register should have a value of 4 at [4:0].

There is slight misunderstanding here,

We are referring to link frequency at 216 MHZ or clock ,

the lane speed is 2 * clock with is 432 

We have changed the EVM board, and Modified the driver w.rt to rpi code . With above change the device is working fine.

Thanks for the support