TDA4AEN-Q1: pin package delay needed for LPDDR

Attached.

7220.J722S_TDA4VEN_TDA4AEN_AM67_Pkg_DDR_Net_Delay_Report.csv

this file doesn't have the csn_0_1/csn_1_1 and it has extra pins that are not on the chp (ddr0_atb0, ddr0_atb1, ddr0_bg1.  the csn that is in the list only says ddr0_cs0_n and ddr0_cd1_n, no indication which csn it is.   what is the explanation of the pin delays NOT on the eval board design PROC170?

This is because the early data manual has the pins mis-labeled.  So when XLS was created, it has names matching that data manual.

DDR0_RAS_N (pin M3) is actually DDR0_CSN0_1

DDR0_CAS_N (pin M4) is actually DDR0_CSN1_1

don't you have a version with the pin numbers?  

We have not updated the file since creation.  We don't have version with pin numbers included.  The file contains pin name and package delay only.

so why aren't these pin delays on the Eval board PROC170?  

Sorry - I'm not understanding your question.  The CVS spreadsheet are package delays not PCB board delays from PROC170.

i based my layout on the eval board layout of the PROC170 board (for TDA4AEN-Q1).  the app note strongly encourages exact copy of the eval board for best results.    the board file for the eval board doesn't have any pin delays on the signals.   this is concerning.

after looking at the routing spec's it looks like the pin delays are all within the routing tolerance, so they're not really need in the routing.

We use Allegro for our PCB designs, but we typically don't use Allegro for our timing analysis.  Since we are designing the DDR controller, we use much more complex circuit tools when looking at timing. That may be why the information is not included in Allegro design.

I'm not familiar with all of the Allegro's constraint manager features - didn't know package delays could be added to PCB delays to create a total delay.  I think that is what you are discussing would be helpful for you/customers.

it is standard procedure to include pin delays of package products especially for ddr's of all types.  the pin delays can be significant in fpga controllers.  it allegro also includes vias in all calculations.

Yes - I was aware of via delay, but thanks for the input regarding package/pin delays.