AM620-Q1: How to reduce operation clock in MCUSS?

Hello Gibbs,

I am routing your query to Linux experts.

As per clock tree tool, we can change the frequency to a 200MHz clock for the M4F.

If you are not able to change the 200MHz clock.

We need to set the parent clock for 200MHz, then set the clock frequency to 200MHz.

This way it should work.

Regards,

Anil.

Hi, Anil

Thanks you replies.

I try to use clock tree to configure M4F clock, setting as below.

* untitled.syscfg

 * Write custom configuration values to the imported modules.
 */
const PLL1                  = system.clockTree["MCU_pllfracf2_ssmod_16fft0"];
PLL1.FB_DIV_INT_DivideValue = 24;

REGISTER SETTING

May I know how to modify (change) this setting in u-boot or linux code?

Thank You.

Gibbs

Hello Gibbs,

To answer the original question: Yes, you can set different frequencies for the M4 core in the Linux devicetree file. However, this will be a static frequency. We do not support dynamically changing the M4F core frequency during runtime.

Do you still want to change the M4F core frequency to be a fixed 200MHz?

Or if the frequency cannot be changed during runtime, do you want to leave the frequency at 400MHz?

Regards,

Nick

Hi, Nick

We understood frequency cannot be changed during runtime, that's ok.

We want to set different frequencies for the M4 core w/ static setting.

M4F core frequency to be a fixed 200MHz is one of our option, because we want to know how to reduce M4 working frequency to reduce power consumption.

I know it is tradeoff between M4 performance and power consumption, 

I even use k3conf to set M4 frequency, but it does not change.

So we need you help to tech us how to set frequencies for M4 in Linux DTS or u-boot

Thank You.

Gibbs

Hello Gibbs,

Understood.

This response will be a bit vague because I am running out of time in the workday. Let me know if you need more information tomorrow.

These instructions are assuming that the M4F clock settings are similar to the PRU clock settings.

Clock tree tool is the right starting point to understand the clock sources that you would need to adjust. I would suggest pulling up the actual M4F core instead of the PLL. In the Left-hand menu, go to processors and accelerators > M4F.

Once you understand which clocks you want to adjust, and what frequencies you want to set them to, then I would expect that we set the clock frequency using the "clocks" entry in the Linux devicetree file. I don't see a "clocks" entry for M4F from a quick search, so you might need to add it.

You can find the clock IDs for each of the clocks, PLL outputs, etc in the TISCI docs here:
https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html

and then you can find a bunch of basic concepts in this documentation I wrote for the PRU clocks:
[FAQ] PRU_ICSSG: How to check and set PRU Core Frequency in Linux?

Regards,

Nick

Hello Nick,

Thanks your replies.

Update status, progress, and need your suggedtion.

I have done (studied) two case of today.

Case 1 : Try to direct modify register setting w/o modification Linux DTS, and check M4F operation frequency clock changes or not.

Case 2 : Base on you information, and try to add node property in Linux DTS

Case 1 , steps as below : 

(1) Check MCU_M4FSS0* clock

root@am62xx-lp-evm:~# k3conf dump clocks | grep EV_MCU_M4FSS0                                                                                                                   
|     8     |     0    | DEV_MCU_M4FSS0_CBASS_0_CLK                                                                           | CLK_STATE_READY     | 200000000       |         
|     9     |     0    | DEV_MCU_M4FSS0_CORE0_DAP_CLK                                                                         | CLK_STATE_READY     | 200000000       |         
|     9     |     1    | DEV_MCU_M4FSS0_CORE0_VBUS_CLK                                                                        | CLK_STATE_READY     | 400000000       |         
|     9     |     2    | DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK                     | CLK_STATE_READY     | 400000000       |         
|     9     |     3    | DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2                    | CLK_STATE_READY     | 200000000       |

(2) Change HSDIV setting from 6 to 16 in clock tree, and generate register setting sets.

(3) Direct register setting

root@am62xx-lp-evm:~# devmem2 0x04040080
/dev/mem opened.
Memory mapped at address 0xffffb577d000.
Read at address  0x04040080 (0xffffb577d080): 0x00008005
root@am62xx-lp-evm:~# devmem2 0x04040080 w 0x0000801f
/dev/mem opened.
Memory mapped at address 0xffff9291b000.
Read at address  0x04040080 (0xffff9291b080): 0x00008005
Write at address 0x04040080 (0xffff9291b080): 0x0000801F, readback 0x0000801F
root@am62xx-lp-evm:~# 
root@am62xx-lp-evm:~# devmem2 0x04040080                                                                                                                                       
/dev/mem opened.                                                                                                                                                               
Memory mapped at address 0xffff9f20a000.                                                                                                                                       
Read at address  0x04040080 (0xffff9f20a080): 0x0000801F 

(4) Check MCU_M4FSS0* clock again, it seems take effort

root@am62xx-lp-evm:~# k3conf dump clocks | grep EV_MCU_M4FSS0                                                                                                                   
|     8     |     0    | DEV_MCU_M4FSS0_CBASS_0_CLK                                                                           | CLK_STATE_READY     | 75000000        |         
|     9     |     0    | DEV_MCU_M4FSS0_CORE0_DAP_CLK                                                                         | CLK_STATE_READY     | 75000000        |         
|     9     |     1    | DEV_MCU_M4FSS0_CORE0_VBUS_CLK                                                                        | CLK_STATE_READY     | 150000000       |         
|     9     |     2    | DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK                     | CLK_STATE_READY     | 150000000       |         
|     9     |     3    | DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2                    | CLK_STATE_READY     | 75000000        | 

Question : How do I make sure it real take effort to reduce operation clock for M4SS ?

Case 2 , steps as below : 

(1) Reference device ID & clock ID as below.

https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html#device-wise-clock-id-list-for-am62x-soc

(2) Modify device tree.

k3-am62-mcu.dtsi

device id set 9, clock id set <9 1>, partent id set <9 2>

	mcu_m4fss: m4fss@5000000 {
		compatible = "ti,am64-m4fss";
		reg = <0x00 0x5000000 0x00 0x30000>,
		      <0x00 0x5040000 0x00 0x10000>;
		reg-names = "iram", "dram";
		resets = <&k3_reset 9 1>;


		/* Gibbs@202050828 */
		clocks = <&k3_clks 9 1>;
		assigned-clocks = <&k3_clks 9 1>;
		assigned-clock-parents = <&k3_clks 9 2>;
		assigned-clock-rates = <200000>;


		firmware-name = "am62-mcu-m4f0_0-fw";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <9>;
		ti,sci-proc-ids = <0x18 0xff>;
		status = "disabled";
	};

Question : 

1. Does the DTS modification correct?

2. I feel very confuse, How to map these parameter as below to TRM (register) ? because I can not search right information.

* DEV_MCU_M4FSS0_CBASS_0_CLK

* DEV_MCU_M4FSS0_CORE0_DAP_CLK

* DEV_MCU_M4FSS0_CORE0_VBUS_CLK

* DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK

* DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2

3. Does it mean only success change in Linux MCU DTS, and then it will appear in "kernel clk_summary" result?

Thank You Very Much

Gibbs

Hello Gibbs,

I will try to set aside some time on Friday to dig into the clock tree and see if your settings look correct. Please ping the thread on Monday if I have not replied by then.

Regards,

Nick

Hello, Nick

Wait your feed back.

Could you give us any comment?

Thank You.

Gibbs

Hello, Nick

Wait your replies, and update some conslusions & question what I found in recent days, because my customer also tracking(+learning from) this thread.

* How to map CLOCK TREE and k3config dump result for M4F core?

root@am62xx-lp-evm:~# k3conf dump clocks | grep EV_MCU_M4FSS0                                                                                                                   
|     8     |     0    | DEV_MCU_M4FSS0_CBASS_0_CLK                                                                           | CLK_STATE_READY     | 200000000       |         
|     9     |     0    | DEV_MCU_M4FSS0_CORE0_DAP_CLK                                                                         | CLK_STATE_READY     | 200000000       |         
|     9     |     1    | DEV_MCU_M4FSS0_CORE0_VBUS_CLK                                                                        | CLK_STATE_READY     | 400000000       |         
|     9     |     2    | DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK                     | CLK_STATE_READY     | 400000000       |         
|     9     |     3    | DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2                    | CLK_STATE_READY     | 200000000       |

(1) DEV_MCU_M4FSS0_CBASS_0_CLK, Ref.

(2) DEV_MCU_M4FSS0_CORE0_VBUS_CLK, Ref

(3) DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK (400MHz)

(4) DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK (200MHz)

so "MCU_M4SS_CLKSEL" is in register "0x0450 8040" bit 0 for selection. 

Because "k3conf" only dump these clock setting, so I think we can "only change" "DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK " or "DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV2_CLK_CLK" for MCU_M4SS0_CORE VBUS_CLOCK setting. So the VBUS_CLOCK should be only for 200MHz or 400MHz.

If you want to modify another clock rate, you must manual modify "hsdiv_clockout0" by setting MCU_PLL0_HSDIV_A (0x04040080)

But I think it should be have some side effect, because you may also change DM R5 Clock setting ... etc

* How to modify Linux DTS?

(1) Update Linux kernel image

(2) Update dtbo

ti-processor-sdk-linux-am62xx-evm-10.01.10.04/targetNFS/boot/dtb/ti$ sudo cp -f *.dtbo /media/gibbs/root/boot/dtb/ti/
ti-processor-sdk-linux-am62xx-evm-10.01.10.04/targetNFS/boot/dtb/ti$ sudo cp -f Image /media/gibbs/root/boot/

I think my setting should be correct, update as below. but it does not work.

Because once DTS setting correct, it should be appear in clock tree summary (/sys/kernel/debug/clk)

	mcu_m4fss: m4fss@5000000 {
		compatible = "ti,am64-m4fss";
		reg = <0x00 0x5000000 0x00 0x30000>,
		      <0x00 0x5040000 0x00 0x10000>;
		reg-names = "iram", "dram";
		resets = <&k3_reset 9 1>;


		/* Gibbs@20250828 */
		clocks = <&k3_clks 9 1>;
		assigned-clocks = <&k3_clks 9 1>;
		assigned-clock-parents = <&k3_clks 9 2>;
		assigned-clock-rates = <200000000>;


		firmware-name = "am62-mcu-m4f0_0-fw";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <9>;
		ti,sci-proc-ids = <0x18 0xff>;
		status = "disabled";
	};

* Is it possible to direct modify register setting for remoteproc drivers (ti_k3_m4_remoteproc.c)?

I not sure this is an good idea, May we use "roremap()" to direct "hard code" setting register w/o Linux DTS?

Any sample code?

Need you suggestion?

Thank You Very Much

GIbbs

Hello, Nick

Wait your replies, and update some conslusions & question what I found in recent days, because my customer also tracking(+learning from) this thread.

* How to map CLOCK TREE and k3config dump result for M4F core?

root@am62xx-lp-evm:~# k3conf dump clocks | grep EV_MCU_M4FSS0                                                                                                                   
|     8     |     0    | DEV_MCU_M4FSS0_CBASS_0_CLK                                                                           | CLK_STATE_READY     | 200000000       |         
|     9     |     0    | DEV_MCU_M4FSS0_CORE0_DAP_CLK                                                                         | CLK_STATE_READY     | 200000000       |         
|     9     |     1    | DEV_MCU_M4FSS0_CORE0_VBUS_CLK                                                                        | CLK_STATE_READY     | 400000000       |         
|     9     |     2    | DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK                     | CLK_STATE_READY     | 400000000       |         
|     9     |     3    | DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2                    | CLK_STATE_READY     | 200000000       |

(1) DEV_MCU_M4FSS0_CBASS_0_CLK, Ref.

(2) DEV_MCU_M4FSS0_CORE0_VBUS_CLK, Ref

(3) DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK (400MHz)

(4) DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK (200MHz)

so "MCU_M4SS_CLKSEL" is in register "0x0450 8040" bit 0 for selection. 

Because "k3conf" only dump these clock setting, so I think we can "only change" "DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK " or "DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV2_CLK_CLK" for MCU_M4SS0_CORE VBUS_CLOCK setting. So the VBUS_CLOCK should be only for 200MHz or 400MHz.

If you want to modify another clock rate, you must manual modify "hsdiv_clockout0" by setting MCU_PLL0_HSDIV_A (0x04040080)

But I think it should be have some side effect, because you may also change DM R5 Clock setting ... etc

* How to modify Linux DTS?

(1) Update Linux kernel image

(2) Update dtbo

ti-processor-sdk-linux-am62xx-evm-10.01.10.04/targetNFS/boot/dtb/ti$ sudo cp -f * /media/gibbs/root/boot/dtb/ti/
ti-processor-sdk-linux-am62xx-evm-10.01.10.04/targetNFS/boot$ sudo cp -f Image /media/gibbs/root/boot/

I think my setting should be correct, update as below. but it does not work.

Because once DTS setting correct, it should be appear in clock tree summary (/sys/kernel/debug/clk)

	mcu_m4fss: m4fss@5000000 {
		compatible = "ti,am64-m4fss";
		reg = <0x00 0x5000000 0x00 0x30000>,
		      <0x00 0x5040000 0x00 0x10000>;
		reg-names = "iram", "dram";
		resets = <&k3_reset 9 1>;


		/* Gibbs@20250828 */
		clocks = <&k3_clks 9 1>;
		assigned-clocks = <&k3_clks 9 1>;
		assigned-clock-parents = <&k3_clks 9 2>;
		assigned-clock-rates = <200000000>;


		firmware-name = "am62-mcu-m4f0_0-fw";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <9>;
		ti,sci-proc-ids = <0x18 0xff>;
		status = "disabled";
	};

* Is it possible to direct modify register setting for remoteproc drivers (ti_k3_m4_remoteproc.c)?

I not sure this is an good idea, May we use "roremap()" to direct "hard code" setting register w/o Linux DTS?

Any sample code?

Need you suggestion?

Thank You Very Much

GIbbs

Hello, Nick

Update status.

I think Linux DTS setting for M4FSS0_CORE0_VBUS_CLK already tale effort, because I can see it in "clock tree summary"

 clk:9:3                             0       0        0        200000000   0          0     50000      Y   deviceless                      no_connection_id         
 clk:9:2                             0       0        0        400000000   0          0     50000      Y   deviceless                      no_connection_id         
    clk:9:1                          0       0        0        400000000   0          0     50000      Y      deviceless                      no_connection_id         
 epwm_tbclk2                         0       0        0        0           0          0     50000      N   deviceless                      no_connection_id         
 epwm_tbclk1                         0       0        0        0           0          0     50000      N   deviceless                      no_connection_id         
 epwm_tbclk0                         0       0        0        0           0          0     50000      N   deviceless                      no_connection_id         
 clk-0                               0       0        0        12288000    0          0     50000      Y   deviceless                      no_connection_id  

But even I change "assigned-clock-parents = <&k3_clks 9 2>" or " assigned-clock-parents = <&k3_clks 9 3>", the M4FSS0_CORE0_VBUS_CLK always keep 400MHZ, Does it have any wrong setting in DTS? Please give us any suggestion.

		/* Gibbs@20250828 */
		clocks = <&k3_clks 9 1>;
		assigned-clocks = <&k3_clks 9 1>;
		assigned-clock-parents = <&k3_clks 9 3>;
		assigned-clock-rates = <200000000>;

		/* Gibbs@20250828 */
		clocks = <&k3_clks 9 1>;
		assigned-clocks = <&k3_clks 9 1>;
		assigned-clock-parents = <&k3_clks 9 2>;
		assigned-clock-rates = <200000000>;

Thank You.

GIbbs

Hi, Nick

I studied & tested few days, so far no update in my side.

My progress,

I try to reduce MCU_PLL0_HSDIV0 clock, and restart MCU firmware, I found it caused firmware crash.

Do you have any new update?

Thank You Very Much

Gibbs

Hello Gibbs,

Thank you for your patience here, and your persistence in pinging me.

Heads up, I had a death in the family recently, so I will be out of office on Friday & Monday. I am spending some time looking at your thread today, and I will respond again on Thursday before I am out.

Are we looking at the right clocks? 

Yes.

https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html#device-wise-clock-id-list-for-am62x-soc only lists 2 input clocks, the DAP clock and the VBUS clock. The DAP clock is just for debug and trace. So we should be looking at the VBUS_CLK input.

I expect that the 2 input clocks are from the MCU_SYSCLK0 input to MCU_M4FSS_CLKSEL. So they should allow us to select between frequency MCU_PLL0_HSDIV_A_clkout0 (400MHz by default), and MCU_PLL0_HSDIV_A_clkout0/2.

Double-checking, is 200MHz ok with the customer at this point? 

If so, that (should be) pretty easy for us to select the other input to MCU_M4FSS_CLKSEL.

Looking at the Linux devicetree file settings 

No need to set frequency here. We should be ok to just select the input clock.

I would expect it to look like this (did not have time to test today):

		clocks = <&k3_clks 9 2>,
		         <&k3_clks 9 3>;
		assigned-clocks = <&k3_clks 9 1>;
		assigned-clock-parents = <&k3_clks 9 3>;

Now does swapping the assigned-clock-parents change the frequency of the M4F core?

Regards,

Nick

Hi, Nick

Follow your comment.

I think test result is the samem, frequency does not change.

		/* Gibbs@20250828 */
		clocks = <&k3_clks 9 2>,
				 <&k3_clks 9 3>;
		assigned-clocks = <&k3_clks 9 1>;
		assigned-clock-parents = <&k3_clks 9 3>;
		assigned-clock-rates = <100000000>;

Thank You.

Gibbs

Hello, Nick

May I have your comment?

Thank You.

Gibbs