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TDA4VH-Q1: PCIe refclk output, termination resistor placement

SH
Intellectual 380 points
Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Tool/software:

What is the recommended placement for the 50ohm termination resistors on PCIe REFCLK_P/REFCLK_N when REFCLK is used as output from TDA4VH SoC to the peripheral?

We are simulating PCIe REFCLK with Hyperlynx and using standard SERDES models to generate 100MHz differential clock.

When placing the 50ohm termination resistors close to the SoC as suggested by Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface (spracp4a) and TDA4VH EVM design we get the following signal waveform: 

But when removing the termination resistors from close to the SoC and placing them next to the peripheral (receiver) we get the following signal waveform, which looks more like what would be expected.

Is TDA4VH PCIE_REFCLK output different in this case that the termination resistors should still be close to SoC (transmitter) and not close to peripheral (receiver)?

If so, would you have simulation model PCIE_REFCLK?

  • 0
    TI__Guru 52065 points

    The PCIe_REFCLK driver IO is similar to HCSL and requires 50-ohms to GND near the source.  To confirm - you have 50-ohm resistor to GND on each P and N clock signal?  Also you routed in such a way not to create stub nets (route the trace through the resistor pad and not to the resistor pad?

  • 0 in reply to Robert Eschler
    Intellectual 380 points

    Yes, that is correct on this design.

    Would you have the IBIS model for the PCIe_REFCLK driver?

  • 0 in reply to SH
    TI__Guru 52065 points

    Sorry for slow response - I was searching for a simulation model.  Its not found in the standard IBIS and its not included in the IBIS_AMI models for the SERDES.  Another note is the waveform results may also be dependent on any other termination included in the circuit - like if the REFCLK receiver has termination enable.