Tool/software:
This is a continuation of the following E2E thread:
AM6442: MCU Plus SDK CPSW Ethernet Examples on Cortex-R5F0_1 Core
...whereby the customer wants to run the CPSW Ethernet examples on Cortex-R5F0_1 Core, and needs to change the DMA resource ownership using the TI SCI interface to the device manager. In the other thread, customer used a modified SBL flow to update the DMA resource ownership. Now, the customer wants to switch to a U-Boot (SPL) flow to do the same. The expected boot flow would look something like this:
- R5 ROM
- SPL Loaded R5, SYSFW loaded to DMSC
- R5 SPL configs DDR and starts A53
- SPL runs on A53
- U-Boot runs on A53
- GHS Integrity runs on A53
- Integrity uses their equivalent of "remote proc" to load and start the R5F0_1 core
...and yes, we are aware that the "SPL" images are also technically cut down configurations of U-Boot.
Our assumption going in is that one of the Device Tree configurations (R5 SPL, A53 SPL, A53 U-Boot, or GHS Integrity) could be modified to setup the DMA resource ownership, rather than writing custom code to make the appropriate TI SCI Client calls. After reviewing the U-Boot DTS and source files, I'm not so sure if that is possible or not.
In this boot flow, where would we expect the DMA resource ownership to be setup? Do we have any similar examples that we can look at for a reference?
Thanks,
Stuart