PROCESSOR-SDK-AM62X: SDL DCC R5

W Z

Expert 2400 points

Part Number: PROCESSOR-SDK-AM62X
Other Parts Discussed in Thread: SK-AM62

Tool/software:

MCU SDK version: mcu_plus_sdk_am62x_10_01_00_33

Test EVM: SK-AM62

CCS version: 12.8.1

I imported the example from C:\ti\mcu_plus_sdk_am62x_10_01_00_33\examples\sdl\dcc\dcc_modes\am62x-sk\r5fss0-0_freertos\

Then, I compiled the R5 projects and copied the generated appimage.hs_fs into the below path.

--file=sbl_prebuilt/am62x-sk/WZ_Debug/dcc_am62x-sk_r5fss0-0_freertos_ti-arm-clang.appimage.hs_fs --operation=flash --flash-offset=0xA00000

I use the file below to flash the test examples.

default_sbl_ospi_hs_fs-r5.cfg

Below is the UART log from SBL UART

SYSFW Firmware Version 10.1.8--v10.01.08 (Fiery Fox)
SYSFW Firmware revision 0xa
SYSFW ABI revision 4.0

[BOOTLOADER_PROFILE] Boot Media       : FLASH 
[BOOTLOADER_PROFILE] Boot Media Clock : 166.667 MHz 
[BOOTLOADER_PROFILE] Boot Image Size  : 175 KB 
[BOOTLOADER_PROFILE] Cores present    : 
m4f0-0
r5f0-0
[BOOTLOADER PROFILE] System_init                      :       5491us 
[BOOTLOADER PROFILE] Board_init                       :          0us 
[BOOTLOADER PROFILE] Drivers_open                     :        301us 
[BOOTLOADER PROFILE] Board_driversOpen                :       1260us 
[BOOTLOADER PROFILE] Sciclient Get Version            :      10202us 
[BOOTLOADER PROFILE] App_waitForMcuPbist              :       8663us 
[BOOTLOADER PROFILE] App_waitForMcuLbist              :       7689us 
[BOOTLOADER PROFILE] App_loadImages                   :       3327us 
[BOOTLOADER PROFILE] App_loadSelfcoreImage            :       4041us 
[BOOTLOADER_PROFILE] SBL Total Time Taken             :      40979us 

Image loading done, switching to application ...
Starting MCU-m4f and 2nd stage bootloader

SYSFW Firmware Version 10.1.8--v10.01.08 (Fiery Fox)
SYSFW Firmware revision 0xa
SYSFW ABI revision 4.0

[BOOTLOADER_PROFILE] Boot Media       : FLASH 
[BOOTLOADER_PROFILE] Boot Media Clock : 166.667 MHz 
[BOOTLOADER_PROFILE] Boot Image Size  : 408 KB 
[BOOTLOADER_PROFILE] Cores present    : 
hsm-m4f0-0
r5f0-0
a530-0
[BOOTLOADER PROFILE] System_init                      :       2789us 
[BOOTLOADER PROFILE] Board_init                       :          1us 
[BOOTLOADER PROFILE] Drivers_open                     :        386us 
[BOOTLOADER PROFILE] Board_driversOpen                :        139us 
[BOOTLOADER PROFILE] Sciclient Get Version            :      10225us 
[BOOTLOADER PROFILE] App_loadImages                   :       2690us 
[BOOTLOADER PROFILE] App_loadSelfcoreImage            :       5349us 
[BOOTLOADER PROFILE] App_loadA53Images                :       4116us 
[BOOTLOADER_PROFILE] SBL Total Time Taken             :      25698us 

Image loading done, switching to application ...
Starting RTOS/Baremetal applications
NOTICE:  BL31: v2.11.0(release):REL.MCUSDK.K3.10.01.00.33
NOTICE:  BL31: Built : 04:57:09, Dec 19 2024

Below is the UART log from DM UART

[15:15:23.569]收←◆Sciserver Testapp Built On: Dec 19 2024 04:51:59
Sciserver Version: v2024.12.0.0-REL.MCUSDK.K3.10.01.00.33+
RM_PM_HAL Version: v10.01.08
Starting Sciserver..... PASSED

 DCC Example Test Application

DCC_Test_init: Init WKUP ESM complete 


USECASE: 0
Source clock: HFOSC0 
Test clock: SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt

Question: How to make this DCC R5 example run?

I can run the DCC M4F successfully C:\ti\mcu_plus_sdk_am62x_10_01_00_33\examples\sdl\dcc\dcc_modes\am62x-sk\m4fss0-0_nortos\

Below is the log.

But it cannot run successfully in the DM core

[BLAZAR_Cortex_M4F_0] 
 DCC Example Test Application

DCC_Test_init: Init WKUP ESM complete 


USECASE: 0
Source clock: HFOSC0 
Test clock: SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt 
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt 
SDL DCC EXAMPLE TEST: Indicating clock drift/change 
UC-0 Completed Successfully

USECASE: 1
Source clock: HFOSC0 
Test clock: SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: DCC Generated completion interrupt 
SDL DCC EXAMPLE TEST: No Clock Drift was observed 
UC-1 Completed Successfully

USECASE: 2
Source clock: HFOSC0 
Test clock: SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and running for some time 
UC-2 Completed Successfully

USECASE: 3
Source clock: RC OSC 
Test clock: SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: DCC Generated completion interrupt 
SDL DCC EXAMPLE TEST: No Clock Drift was observed 
UC-3 Completed Successfully

USECASE: 4
Source clock: RC OSC 
Test clock: SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt 
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt 
SDL DCC EXAMPLE TEST: Indicating clock drift/change 
UC-4 Completed Successfully

USECASE: 5
Source clock: RC OSC 
Test clock: SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt 
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt 
SDL DCC EXAMPLE TEST: Indicating clock drift/change 
UC-5 Completed Successfully

USECASE: 6
Source clock: RC OSC 
Test clock: SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt 
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt 
SDL DCC EXAMPLE TEST: Indicating clock drift/change 
UC-6 Completed Successfully

USECASE: 7
Source clock: HFOSC0 
Test clock: MAIN_SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt 
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt 
SDL DCC EXAMPLE TEST: Indicating clock drift/change 
UC-7 Completed Successfully

USECASE: 8
Source clock: RC OSC 
Test clock: MAIN_SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and running for some time 
UC-8 Completed Successfully

USECASE: 9
Source clock: HFOSC0 
Test clock: FICLK

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and running for some time 
UC-9 Completed Successfully

USECASE: 10
Source clock: FICLK 
Test clock: MAIN_SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and running for some time 
UC-10 Completed Successfully

 All tests have passed.

7 months ago

0 W Z 7 months ago

Expert 2400 points

Could a TI expert help?

0 Nihar Potturu 7 months ago in reply to W Z

TI__Mastermind 26226 points

Hello,

There seems to be some issue with DCC example on R5 in the 10.1 MCU+SDK. I am running into a similar issue.

However, the example is running as expected in the latest 11.1 SDK.

Can you try running that example and check if you run into the same issue.

https://www.ti.com/tool/download/MCU-PLUS-SDK-AM62X/11.01.00.16

Regards,

Nihar Potturu

+1 Nihar Potturu 7 months ago in reply to Nihar Potturu

TI__Mastermind 26226 points

Update : Increasing the SVC stack size in the linker.cmd file fixed the issue. This seems to be some stack overflow problem causing the R5F core to go into prefetch abort state. Can you increasing the SVC stack size and check if that fixes the issue.

Regards,

Nihar Potturu

0 W Z 7 months ago in reply to Nihar Potturu

Expert 2400 points

Do you mean this?

__SVC_STACK_SIZE = 0x0100; /* This is the size of stack when R5 is in SVC mode */

I am trying to increase it to __SVC_STACK_SIZE = 0x0200; /* This is the size of stack when R5 is in SVC mode */

0 W Z 7 months ago in reply to W Z

Expert 2400 points

Your update tip is right.

After change __SVC_STACK_SIZE from 0x100 to 0x200, it works.

0 W Z 7 months ago in reply to Nihar Potturu

Expert 2400 points

But I checked the example dcc_am62x-sk_r5fss0-0_freertos_ti-arm-clang in mcu_plus_sdk_am62x_11_00_00_16.

The __SVC_STACK_SIZE is 0x100. Why can this example work?

Does complier bring in the difference?

I use the mcu_plus_sdk_am62x_11_00_00_16. with CCS 20.1.1.

The mcu_plus_sdk_am62x_10_01_00_33. with Code Composer Studio 12.8.1.

The project team had decided to use the mcu_plus_sdk_am62x_10_01_00_33. with Code Composer Studio 12.8.1.

0 Nihar Potturu 7 months ago in reply to W Z

TI__Mastermind 26226 points

Hello,

The issue would be most likely with the DM firmware. The stack must be overflowing while processing some of the DM requests. There have been a few updates in the DM firmware in the 11.0 SDK which would have fixed the issue.

Regards,

Nihar Potturu

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PROCESSOR-SDK-AM62X: SDL DCC R5