PROCESSOR-SDK-J784S4: PSDK SERDES CONFIGURATION

Hi,

Jonas Mohrs said:

In the function CSL_serdesRefclkSel it seems that the bit PMA_CMN_REFCLK1_INT_MODE of wiz16b8m4ct3_WIZ16B8M4CT3_WIZ_CONFIG_SERDES_TOP_CTRL will only be set if the user has chosen CSL_SERDES_REF_CLOCK_INT1 as the reference clk source.

Yes.

You can find the condition above refClkSrc is compared with REF_CLOCK_INT1 then only above code will execute/run.

Jonas Mohrs said:

However in the description of the bitfield I do not understand the connection to the chosen reference clock. From my understanding this bit should be set as soon as you chose a ref clk with >= 100MHz.

You can find the below from Register Spec, above is to choose the mode of operation of reference clock as >100MHz or Lower.


Best Regards,
Sudheer

Hi,
this is not answering my question.

The clock is set to 100MHz and the driver is not properly setting this bit.

HI, 

Jonas Mohrs said:

The clock is set to 100MHz and the driver is not properly setting this bit.

If clock is set to 100MHz, as per code shared top_ctrl was set with 1, which is valid as per register specification. 

Why you are not using ref clock instead of ref1clk. 

If it is a single link we recommend to use refclk. 

Can you please share more details about your concern, if your concern was not addresses. 

Best Regards, 

Sudheer

In the driver I configured to use INT0 however the driver only sets the bit for INT1. And I do not see this distinction in the datasheet.

Hi,

Jonas Mohrs said:

In the driver I configured to use INT0 however the driver only sets the bit for INT1. And I do not see this distinction in the datasheet.

How are you passing the refclock INT0?
You should use it as per below.

serdesLaneEnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT0;