Tool/software:
Champs,
customer has RGMII connecting directly to a switch chip that has its own PHY hence not using MDIO. what's the best way to separate RGMII from PHY in the drier in this case?
thank you
Michael
Tool/software:
Champs,
customer has RGMII connecting directly to a switch chip that has its own PHY hence not using MDIO. what's the best way to separate RGMII from PHY in the drier in this case?
thank you
Michael
Hello Michael
Thank you for the query.
I have been assigned this query.
Based on the above, i assume the query is related to the CPSW MAC interface software.
Can you please confirm my understanding is current and provide inputs on the software development customer is using for the AM62D.
Regards,
Sreenivasa
Hi Michael,
Network is out of my expertise, but referring to other similar work, it seems mac-to-mac in Linux can be achieved by simply removing the PHY node from the CPSW node. Following is the kernel devicetree patch for reference.
diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts index e766b8a9583f..861950e417f9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -640,35 +640,11 @@ cpts@3d000 { &cpsw_port1 { status = "okay"; phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy0>; }; &cpsw_port2 { status = "okay"; phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy1>; -}; - -&cpsw3g_mdio { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mdio0_pins_default>; - - cpsw3g_phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,min-output-impedance; - }; - - cpsw3g_phy1: ethernet-phy@3 { - reg = <3>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,min-output-impedance; - }; }; /* main_rti4 is used by C7x DSP */
yes, it is about CPSW MAC to MAC interface without phy and MDIO. We are aware of the device tree change and it is not enough, since MDIO and PHY drivers are tighten together with TI's CPSW ethernet driver, you will see the following log and ethernet not up and not working.
[ 1.392907] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[ 1.392921] davinci_mdio 8000f00.mdio: no live phy, scanning all
[ 1.493074] davinci_mdio 8000f00.mdio: timed out waiting for user access
[ 1.593454] davinci_mdio 8000f00.mdio: timed out waiting for idle
[ 1.593467] davinci_mdio 8000f00.mdio: probe with driver davinci_mdio failed with error -5
[ 1.593568] am65-cpsw-nuss 8000000.ethernet: initializing am65 cpsw nuss version 0x6BA01103, cpsw version 0x6BA81103 Ports: 3 quirks:00000006
[ 1.594027] am65-cpsw-nuss 8000000.ethernet: /bus@f0000/ethernet@8000000/ethernet-ports/port@2 read phy-mode err -22
[ 1.594355] am65-cpsw-nuss 8000000.ethernet: probe with driver am65-cpsw-nuss failed with error -22
From ethernet/ti/Kconfig:
config TI_K3_AM65_CPSW_NUSS
tristate "TI K3 AM654x/J721E CPSW Ethernet driver"
depends on ARCH_K3 && OF && TI_K3_UDMA_GLUE_LAYER
select NET_DEVLINK
select TI_DAVINCI_MDIO
select PHYLINK
select PAGE_POOL
select TI_K3_CPPI_DESC_POOL
imply PHY_TI_GMII_SEL
depends on TI_K3_AM65_CPTS || !TI_K3_AM65_CPTS
If I force disable PHY and MDIO in Kconfig, there are a lot of compile errors.
Thanks Aiping
Hi Aiping,
Instead of removing "&cpsw3g_mdio" node as in my previous patch, I changed its status to "disabled" as in the patch below.
diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts index e766b8a9583f..dba85ccca7a9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -640,17 +640,15 @@ cpts@3d000 { &cpsw_port1 { status = "okay"; phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy0>; }; &cpsw_port2 { status = "okay"; phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy1>; }; &cpsw3g_mdio { - status = "okay"; + status = "disabled"; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default";
I don't see any failure in the kernel boot log. Can you please test with new patch and let me know if this gets CPSW to work on your board?
root@am62dxx-evm:~# dmesg|grep mdio root@am62dxx-evm:~# dmesg|grep nuss [ 1.654354] am65-cpsw-nuss 8000000.ethernet: initializing am65 cpsw nuss version 0x6BA01103, cpsw version 0x6BA81103 Ports: 3 quirks:00000 006 [ 1.654858] am65-cpsw-nuss 8000000.ethernet: Use random MAC address [ 1.654943] am65-cpsw-nuss 8000000.ethernet: initialized cpsw ale version 1.5 [ 1.654950] am65-cpsw-nuss 8000000.ethernet: ALE Table size 512, Policers 32 [ 1.655851] am65-cpsw-nuss 8000000.ethernet: CPTS ver 0x4e8a010c, freq:500000000, add_val:1 pps:1 [ 1.703836] am65-cpsw-nuss 8000000.ethernet: set new flow-id-base 19
[ 1.594027] am65-cpsw-nuss 8000000.ethernet: /bus@f0000/ethernet@8000000/ethernet-ports/port@2 read phy-mode err -22
I am wondering how would you get this error message, as the devicetree still has the phy-mode defined.
phy-mode = "rgmii-rxid";
It turns out the mdio is enabled by default. Simply removing cpsw3g_mdio from the device tree (as suggested by 0001-cpsw2g-nophy.patch) does not solve the problem. &cpsw3g_mdio { status="disabled"}; fixes the issue, and ethernet without PHY is working now
Hi Aiping,
Glad it is working now. Thanks for the update.
&cpsw3g_mdio { status="disabled"}; fixes the issue,
I mentioned this last week:
Instead of removing "&cpsw3g_mdio" node as in my previous patch, I changed its status to "disabled" as in the patch below.