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TDA4VEN-Q1: How do reset ddr?

xie jc
Expert 2180 points
Part Number: TDA4VEN-Q1

Tool/software:

Hi TI experts,

Are these the steps to reset the DDR power supply(ddr_Reset func)？

I am working on compatibility with different DDRs on SBL. When I compile different SBLs using different DDR configurations, executing memtester is normal; After successfully identifying different DDRs through the MR register in sbl, I found that memtester would fail.

I have also provided modifications for DDR compatibility, please help to check them as well.

static int32_t ddr_Reset(void)
{
        Bootloader_profileAddProfilePoint("Resetting DDRSS 0721——2...\n");
        *(volatile unsigned int*)(0x400B20) = (*(volatile unsigned int*)(0x400B20) & 0xFFFFFF00) | 0x1;
        *(volatile unsigned int*)(0x400120) = 0x1;

        while(*(volatile unsigned int*)(0x400128) != 0);

        *(volatile unsigned int*)(0x400B24) = (*(volatile unsigned int*)(0x400B24) & 0xFFFFFF00) | 0x1;
        *(volatile unsigned int*)(0x400120) = 0x1;

        while(*(volatile unsigned int*)(0x400128) != 0);

        *(volatile unsigned int*)(0x400B28) = (*(volatile unsigned int*)(0x400B28) & 0xFFFFFF00) | 0x1;
        *(volatile unsigned int*)(0x400120) = 0x1;

        while(*(volatile unsigned int*)(0x400128) != 0);

        *(volatile unsigned int*)(0x400B20) = (*(volatile unsigned int*)(0x400B20) & 0xFFFFFF00) | 0x3;
        *(volatile unsigned int*)(0x400120) = 0x1;

        while(*(volatile unsigned int*)(0x400128) != 0);

        *(volatile unsigned int*)(0x400B24) = (*(volatile unsigned int*)(0x400B24) & 0xFFFFFF00) | 0x3;
        *(volatile unsigned int*)(0x400120) = 0x1;

        while(*(volatile unsigned int*)(0x400128) != 0);

        *(volatile unsigned int*)(0x400B28) = (*(volatile unsigned int*)(0x400B28) & 0xFFFFFF00) | 0x3;
        *(volatile unsigned int*)(0x400120) = 0x1;

        while(*(volatile unsigned int*)(0x400128) != 0);

        return SystemP_SUCCESS;
}

0001-DDR-2G-2G-DDR-20250704.txt

  • 0
    TI__Expert 3715 points

    Hi Kevin,

    Refer to TDA4VEN DDRSS TRM

    the base address of psc_MDCTL is 0x00400A00 and below is offset of LPSC 72/73/74 which is for DDR32SS0 

    72 x 4 = 0x120

    73 x 4 = 0x124

    74 x 4 = 0x128

    We flow the below steps to reset and enable LPSC 72/73/74, Could you please help to check if this sequence can fully reset DDR32SS0? 

    -1-

    set LPSC to SyncRst through register psc_MDCTL (bit 4:0)

    -2-

    set GO bit to 1 in register psc_PTCMD (0040 0120h)

    -3-

    waiting for cmd done through psc_PTSTAT(0040 0128h)

    -4-

    set LPSC to Enable through register psc_MDCTL (bit 4:0)

    -5-

    set GO bit to 1 in register psc_PTCMD (0040 0120h)

    -6-

    waiting for cmd done through psc_PTSTAT(0040 0128h)

    Regards

    Joe

  • 0
    TI__Mastermind 38370 points

    Hi,

    xie jc said:
    I am working on compatibility with different DDRs on SBL

    What is different in the 2x configurations? (I only see one set of register values in the .txt file that was attached).

    Ideally, if you can provide the DDR register configuration tool input differences, that would be best.

    xie jc said:
    After successfully identifying different DDRs through the MR register in sbl, I found that memtester would fail.

    My understanding is that you are initializing LPDDR4, reading the ID, resetting the DDRSS, then re-initializing the LPDDR4. Is the DDR PLL configured identically before DDR is initialized in both scenarios? (ie., right before initial config and after the DDRSS is reset?)

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Expert 2180 points

    Hi Kervin S,

    Kevin S said:
    What is different in the 2x configurations? (I only see one set of register values in the .txt file that was attached).

    These two DDR configurations are different, one for Micron and the other for Nanya.

    Kevin S said:
    Is the DDR PLL configured identically before DDR is initialized in both scenarios? (ie., right before initial config and after the DDRSS is reset?)

    BR.

  • 0 in reply to xie jc
    Expert 2180 points

    Hi Joe&Kevin S,

    I used two different pieces of hardware and in different situations, I dumped the registers of DDR. Currently, it seems that even if DDR initialization is performed again after executing DDR reset, the configuration content of the previous DDR initialization will still appear.

    DDR_reg_dump.rar

    BR.