AM625: GPIO: Drive Strength Control

Alexander Sverdlin

Part Number: AM625
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Dear TI Engineers!

We would like to explore the possibilities to reduce EMI by reducing the Drive Strength on some GPIO pins.

We've found that there are DRV_STR bits (Drive Strength Control. Selects the drive strength value for LVCMOS pins.) in Pad Configuration Registers, but among the possible values there is only one "default" and 3 "reserved".

Would it be possible to clarify if the values other than "default" 0 are safe to configure and to get some, maybe preliminary information on the other (currently reserved) values?

Alexander.

23 days ago

0 Stanislav Stilyanov 22 days ago

TI__Mastermind 18400 points

Hi Alexander,

DRV_STR bit values are going to enter SysConfig tool in a new version targeted in October. I can check if I can get the values. Should not be a problem, I think.

Regards,

Stan

0 Alexander Sverdlin 22 days ago in reply to Stanislav Stilyanov

Prodigy 60 points

Hi Stanislav and thank you for the quick reply!
I'll appreciate any preliminary info before the official tool release because we are exactly in this phase of HW development where we try to bring EMI levels lower and this will definitely help us!

Alexander.

0 Stanislav Stilyanov 21 days ago in reply to Alexander Sverdlin

TI__Mastermind 18400 points

Hi Alexander,

I got the bit value descriptions:

0 - Nominal
1 - Slow
2 - Fast
3 - Reserved

3 is indeed reserved and should not be selected.

I hope this will help to mitigate your issue.

Regards,

Stan

0 Alexander Sverdlin 21 days ago in reply to Stanislav Stilyanov

Prodigy 60 points

Thank you Stanislav! Much appreciated!

0 Stanislav Stilyanov 21 days ago in reply to Alexander Sverdlin

TI__Mastermind 18400 points

Alexander, you are welcome!

0 Peter Christen 17 days ago in reply to Stanislav Stilyanov

Prodigy 60 points

Dear Stanislav

You mentioned, that at least 3 of 4 values of the DRV_STR bits in the pad configuration register will be supported by the SysConfig tool in future. May I ask, if this change will have any impact on the mentioned CPU GPIO's? Because in [FAQ] AM625 / AM623 / AM620-Q1 / AM62Ax / AM62Px / AM62D-Q1 / AM62L / AM64x / AM243x Design Recommendations / Custom board hardware design - Drive Strength Configuration for SDIO and LVCMOS I/Os a quite opposite opinion is expressed.

Best regards
Peter

0 Stanislav Stilyanov 16 days ago in reply to Peter Christen

TI__Mastermind 18400 points

Hello Peter,

Good question. What I posted here is the functional meaning of the 2 bits. FAQ is still the official recommendation for drive strength until Q4 2025. For example I heard the intention is to add support for Fast for now.

0 Kallikuppa Sreenivasa 16 days ago in reply to Peter Christen

TI__Guru**** 191149 points

Hello Peter,

The recommendation is to follow the FAQ. The FAQ will be updated when the results are available.

The Design and Validation team is currently working (internally simulating) to enable the NOM and FAST drive strength for LVCMOS IOs.

The simulation and test results are expected to be available during Q4 (including being able to configure using sysconfig).

In case you have an use case for testing the fast drive strength, please work with the TI filed team supporting your projects to take the discussion forward.

Regards,

Sreenivasa

0 Peter Christen 16 days ago in reply to Kallikuppa Sreenivasa

Prodigy 60 points

Dear Sreenivasa

Actually we are more interested in the "SLOW" drive strength then in the "FAST" mode. However, we are very interested in the results coming in Q4 2025 and we will stay tuned.

Best regards
Peter

0 Kallikuppa Sreenivasa 16 days ago in reply to Peter Christen

TI__Guru**** 191149 points

Hello Peter,

I will have to check if there is plan to support SLOW drive strength.

Let me check internally.

The LVCMOS IO are 60R nom drive strength.

Help me understand a use case where you need to increase the impedance.

Regards,

Sreenivasa

0 Peter Christen 16 days ago in reply to Kallikuppa Sreenivasa

Prodigy 60 points

Dear Sreenivasa

Basically, we want to reduce radiated emissions coming from too high and unnecessary slew rates. Some nets in our board system do not need such strong drive strengths and therefore these GPIO's shall be configured with SLOW drive strength.

Principle: As little as possible, as much as necessary.

Best regards
Peter

0 Kallikuppa Sreenivasa 15 days ago in reply to Peter Christen

TI__Guru**** 191149 points

Hello Peter,

Thank you for the inputs.

The design and validation teams are targeting currently to support the NOM and FAST drive strength.

Regards,

Sreenivasa

0 jorgen.olsen 1 day ago in reply to Kallikuppa Sreenivasa

Prodigy 175 points

Our project probably also could benefit EMI-wise if the "SLOW" option becomes a possibility

0 Kallikuppa Sreenivasa 1 day ago in reply to jorgen.olsen

TI__Guru**** 191149 points

Hello Jorgen,

Thank you.

Help me understand the use case.

I can provide the feedback to the Design and Validation team to adding the capability in the future.

Regards,

Sreenivasa

0 jorgen.olsen 1 day ago in reply to Kallikuppa Sreenivasa

Prodigy 175 points

Hello Sreenivasa

In a typical system you have a lot of static or semi-static I/O's. These I/O lines when driven from a fast/low impedance output can act an antenna due to induced noise generating currents. If the sourcing impedance is raised the current is reduced and the emitted RF will be lower. Also sourcing not-static lines with signals with a small risetime, generates large currents both in the line and back into the decoupling caps on the I/O driver that also contribute to the emitted noise spectrum. Clearly a lot of signals also needs the full speed of the I/O-port so the other port drive-strengths are also very important. We are analyzing our problem which is in the region of 700-800MHz and some spurious peaks we can do something about using resistors in the line. But still it would be nice to be able to set the parameters in question.

Regards

Jørgen

0 Stanislav Stilyanov 23 hours ago in reply to jorgen.olsen

TI__Mastermind 18400 points

Hi Jorgen,

I believe Sreenivasa provided feedback to validation team.

Regards,

Stan

0 jorgen.olsen 23 hours ago in reply to Stanislav Stilyanov

Prodigy 175 points

Looking forward to having this possibility implemented. Thanks a lot.

Regards

Jørgen

0 Kallikuppa Sreenivasa 23 hours ago in reply to jorgen.olsen

TI__Guru**** 191149 points

Hello Jorgen,

Thank you and appreciate the inputs.

Please follow the below FAQ for any updates. I will update the FAQ as we enable the drive strength support.

The current focus being NOM and FAST for LVCMOS.

Regards,

Sreenivasa

0 Alexander Sverdlin 22 hours ago in reply to Kallikuppa Sreenivasa

Prodigy 60 points

Dear Sreenivasa,

Isn't it so, that 2/2 customers in this thread rather would be happy to have the support for SLOW? ;-)

Alexander.

0 Peter Christen 22 hours ago in reply to Alexander Sverdlin

Prodigy 60 points

I cannot agree more! :-D

0 Kallikuppa Sreenivasa 21 hours ago in reply to Peter Christen

TI__Guru**** 191149 points

HI All,

Thank you for the inputs for the device improvements.

Kallikuppa Sreenivasa said:
The current focus being NOM and FAST for LVCMOS.

This is the current focus on the team and hence wanted to be sure i let you know.

The inputs are appreciated. Let me reach out to the device expert and get his thoughts on the request and the challenges to support Slow drive strength

Regards,

Sreenivasa

Processors

Processors forum

AM625: GPIO: Drive Strength Control