AM620-Q1: AM6204BTGFHIALWRQ1

Hello Surinder Sharma,

Thank you for the query.

Surender Sharma said:

We are using the AM620-Q1 EVM reference schematic in our design. In this schematic, there is a net named “VPP_LDO_EN” which was previously controlled by the I/O expander externally. Now we are not using the I/O expander, where should this signal be connected?

You can connect to any of the SOC IO that are not used. 

With the mapping of VPP_LDO_EN to an IO, there will be changes that may be required to be done i the key writer package.

I understand this is a simple program and allows customer to make the IO mapping changes.

In case you need support, this is something TI could provide.

Regards,

Sreenivasa

Hello Surinder Sharma,

Surender Sharma said:

We are using the PSE2A0SL-08GX eMMC. This eMMC includes a Data Strobe (DS) pin. Currently, we have connected the DS pin to the W18 pin of the SoC (since it is a free pin, as we are using only a single Ethernet channel). Is this the correct connection? If not, please suggest the proper pin to which it should be connected.

Am625 dos not support DS pin.

You can add a pulldown and a TP as a provision for probing.

FYI, CALPAD and DS pins are supported on the eMMC hard macro PHY that supports HS400 speed 

Regards,

Sreenivasa

Hello Surinder Sharma,

I added the connection recommendations for the change list you shared.

GPIO_eMMC_RSTn
Connect to any of the SOC IO to implement local reset.
In case the IO is different from the one used on the SK (uses IO expander), software changes to remap the IO is required

This connection is recommended.

MCU_I2C0
A pullup is required irrespective of IO usage or configuration

Add pullup 4.7K for MCU_I2C_ signals
I2C interface not used
Open-drain output type buffer I2C interfaces have slew rate requirement when pulled to 3.3 V
An RC is recommended for slew rate control
Refer SK-AM62P-LP schematics

IO_EXP_TEST_LED
Place pulldown near to pin 3 of FET
Connect to an SOC IO for indication of 3.3V presence
This is optional

GPIO_OLDI_RSTn
Connect to SOC IO pin for local reset
Configure the software for the used IO

CSI_VLDO_SEL
Connection not visible
Connect to an SOC IO pin
Configure the software based on the selected IO

Connect an SOC IO with a 10K pullup to one of the ANDing logic input for local reset

Connect PORz_OUT and RESETSTATz through separate 0R resistors to the other AND gate input.

Populate 0R for RESETSTATz and DNI series resistor for PORz_OUT initially 

Regards,

Sreenivasa

In your last comments regarding PORz_OUT and RESETSTATz, both signals are connected to multiple AND gates. Therefore, 0Ω resistor is required for each AND gate, so that we can implement only the ones we need. Is this what you meant? Please confirm. Please share the remaining review points as well, so we can implement them simultaneously.

Hello Surinder Sharma,

In the schematics, there is a 2 input AND gate.

Please follow below connection.

Regards,

Sreenivasa

Hello Surinder Sharma,

I will add the review comments for the first pass review completed schematic, Some additional comments may be added while rerevieing but this should help you with continuing the changes.

Page 3
reduce R54 value to 22R
Looks to be a voltage divider now
Reduce package to 0402 for R54 and R56

100V cap used for 12V
Follow below
100nF/50V/0603

C136, C137
10V cap used for 12V supply
Use 25V or above

CAN_TX U8
SOC IO buffers are off during reset
Add parallel pull in case the input can float
Suggest adding a pullup

CAN_VIO_3.3V uC
Net connection is not visible
In case this connect to the SOC connection of a large cap load at the output is not allowed or recommended

BUCK EN CAN
Net not visible

Regards

Sreenivasa

Thanks for the comments.

• CAN_VIO_3.3V uC net is connected to E7 pin of the SoC (Page 20).

• BUCK EN CAN net is connected to U29 load switch (Page 6).

This issue occurred due to a PDF generation, while searching for these context.

Hello Surinder Sharma,

Thank you.

Please refer updated comments 

CAN_VIO_3.3V uC
Connected to SOC IO
Connecting a 100nF cap directly to the SOC output is not recommended
Reduce the cap value to 22pF
Move R148 near to the VIO pin5 of U9

BUCK EN CAN
Connected to U29 load switch EN
PMIC GPIO open daring output is also connected.
SN74AHC1G08 Single 2-Input Positive-AND Gate
Use a open drain output type AND gate

Regards,

Sreenivasa

Hi,

Please explain the BUCK EN CAN connection to U29. Our requirement is that, if in the future we need to control this load switch through the SoC, we should be able to do so.

Is this suggested by you as per the attached picture?

Please confirm.

Hello Surender

The above option is Ok but the gate may not be required.

PMIC GPIO is Open drain output

 SN74AHC1G08 Single 2-Input Positive-AND Gate

choose below 

SN74AHC1G09 Single 2–Input Positive-AND Gate With Open-Drain Output

It is Ok to short 2 open drain outputs and connect a common resistor to perform ANDing. 

 https://e2e.ti.com/support/logic-group/logic/f/logic-forum/865215/faq-with-open-drain-outputs-can-i-use-them-to-shift-a-logic-voltage-level-connect-the-outputs-directly-together-force-a-voltage-node-to-zero 

With an open-drain output, there is no danger of one output being HIGH and another being LOW since all outputs are either LOW or Hi-Z. In the above image we show how three open-drain buffers can be combined to produce a 3-input AND gate function. It is important to note that the output signal has the same limitation as the previous use-case: the signal can either be fast or low power, but not both.

Regards,

Sreenivasa

Hi Sir,

I’m a little confused in this case. Could you please draw the input and output connections of the SN74AHC1G09?

Hello Surender

Thank you.

You can retain the current connections and only replace the AND gate with open drain output type. 

The switch will be enabled when both signals are high.

Please read the FAQ linked above for explanation.

I missed seeing the 0R in your diagram above. 

In case you are considering populating any one of the option, the current design should work. No change.

In case you want to OR both signals, you may have to use an OR gate and connect as you have shown in the above diagram copied below (gate needs to change to OR gate)

Regards,

Sreenivasa

Hello Surender

I added the review comments for Page 5

VPP_1V8 connection to SOC VPP pin
Add a series resistor to the VPP
supply pin for isolation or testing
refer AM62P schematics

VPP_LDO_EN
Connect to any of the SOC IO
This will call for software changes in the key writer program

VPP_1V8
Add an additional decap 0.1 uF
near to the SoC VPP pin

VPP_LDO_EN
Move pulldown near to
EN pin - pin 3 of LDO U18

TLV75518PDQNR
Given challenges with assembly, consider alternate package
Use TLV75518PDBVR
refer AM62L schematics

U56
TLV75510PDQNR
Given challenges with assembly, consider alternate package
Use TLV75510PDBVR

Regards,

Sreenivasa

Hello Surender

I added the review comments for Page 6..10

Page 6
U29
Add a cap (220 pF or higher) to
the CT pin for SoC IO supply slew rate
control. SoC IO supplies have slew rate
requirements specified

PMIC input bulk caps
Add a HF cap across bulk caps

U22
PVIN_B1_1
PVIN_B1_2
Can share same bulk cap

U22 MODE/RESET
RESETSTATz performs warm reset and has no effect on the PMIC
DNI series resistor
PMIC supports internal pull

U22 PMIC buck outputs feedback
Tie the feedback after the DC/DC output bulk caps

U29
Add a cap (220 pF or higher) to
the CT pin for SoC IO supply slew rate
control. SoC IO supplies have slew rate
requirements specified

Page 8
VMON VSYS
Connect 12V supply used to generate 3.3V main supply and adjust divider ratio
Recommend implementing the voltage monitoring functionality using VMON_VSYS
for early detection of supply failure
It is meant to be a power-fail indicator for the main input (higher)
voltage rail that enters the PCB. For example, 5, 12, or 24 volts.
The error associated with this monitor would require you to set the threshold
significantly lower than the nominal to avoid false trigger
Refer System Power Supply Monitor Design Guidelines section of the data sheet

SoC_VDDSHV5_SDIO
Add 1 uF bulk cap

U12Q
Delete TP
RSVD pin
leave unconnected

Page 10
LPDDR4_RESET_N
10 K pulldown is
recommended
Refer Processor
specific DDR design
guide

Regards,

Sreenivasa

PMIC input bulk caps
Add a HF cap across bulk caps

U22
PVIN_B1_1
PVIN_B1_2
Can share same bulk cap

I didn’t get your point. Please suggest the capacitor value to be added between PVIN_B1_1 and PVIN_B1_2.

U22 PMIC buck outputs feedback
Tie the feedback after the DC/DC output bulk caps

Please explain more — is it necessary to add a capacitor to FB_B1, FB_B2, and FB_B3?

Page 8
VMON VSYS
Connect 12V supply used to generate 3.3V main supply and adjust divider ratio
Recommend implementing the voltage monitoring functionality using VMON_VSYS
for early detection of supply failure
It is meant to be a power-fail indicator for the main input (higher)
voltage rail that enters the PCB. For example, 5, 12, or 24 volts.
The error associated with this monitor would require you to set the threshold
significantly lower than the nominal to avoid false trigger
Refer System Power Supply Monitor Design Guidelines section of the data sheet.

I can add 12V for this divider. Please suggest, which lowest voltage monitoring. The 12V is generated from a DC-DC converter, which outputs 8V when its input drops to 8V. If the input falls below 8V, we will cut off the DC-DC supply.

Hello Surender,

I answered the PMIC related queries.

Surender Sharma said:

PMIC input bulk caps
Add a HF cap across bulk caps

Tiy can add a 0.1uF cap 

Surender Sharma said:

U22
PVIN_B1_1
PVIN_B1_2
Can share same bulk cap

I didn’t get your point. Please suggest the capacitor value to be added between PVIN_B1_1 and PVIN_B1_2.

DNI one of the cap

Surender Sharma said:

U22 PMIC buck outputs feedback
Tie the feedback after the DC/DC output bulk caps

Please explain more — is it necessary to add a capacitor to FB_B1, FB_B2, and FB_B3?

(+) [FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM625SIP Design Recommendations / Custom board hardware design – Common queries for PMIC TPS65219 and PDN - Processors forum - Processors - TI E2E support forums

PMIC - feedback connected after the bulk cap

Regards,

Sreenivasa

Hello Surender Sharma, 

Surender Sharma said:

VMON VSYS
Connect 12V supply used to generate 3.3V main supply and adjust divider ratio
Recommend implementing the voltage monitoring functionality using VMON_VSYS
for early detection of supply failure
It is meant to be a power-fail indicator for the main input (higher)
voltage rail that enters the PCB. For example, 5, 12, or 24 volts.
The error associated with this monitor would require you to set the threshold
significantly lower than the nominal to avoid false trigger
Refer System Power Supply Monitor Design Guidelines section of the data sheet.

I can add 12V for this divider. Please suggest, which lowest voltage monitoring. The 12V is generated from a DC-DC converter, which outputs 8V when its input drops to 8V. If the input falls below 8V, we will cut off the DC-DC supply.

I would suggest to little higher voltage (~9.5-10V (outside the normal operating voltage range)). I assume this voltage will be seen only during power failure and not during normal operation

VMON_VSYS is used to detects the failure of the input voltage early for processor to take some action. The action is software dependent and so there is no concern. 

Regards,

Sreenivasa

Hello Surender Sharma

I added the review comments for Page 11..12

Page 11
eMMC_RSTn reset signal ANDing logic ouput
use 10K

GPIO_eMMC_RSTn connection
Connect to any of the SOC IO to implement local reset.
In case the IO is different from the one used on the SK, software changes to remap the IO is required

MMC1_CLK
move pullup near to the SD card socket

EMMC data interface signals
DNI pullup for D1..D3
Refer SK schematics

EMMC data interface signals
DNI pullup for D4..D7
Refer SK schematics

Delete series resistor provision for D0..D7
This can affect eMMC interface performance

eMMC_CLK_18
Add a pulldown 10K
delete pullup 47K

eMMC_DS_18
Reduce to 10K
Add a TP
DS is not supported by eMMC interface

Page 12
U13 QOD
connect through 0R
Adjust R after testing

SD CARD LOAD SWITCH RESET LOGIC
Use RESETSTAtz and SOC IO
SOC IO performs local reset
Add a pullup 10K for the SOC IO input near to the AND gate
Refe SK schematics

SD card interface data and CMD pullup value
Change to 47K
Ensure internal pullups are not configured when 10K external pullups are used. As a good design practice, a
47K pullup is recommended to ensure the pullup value is within the SD card specification, when internal pulls are
enabled unexpectedly. This way the resulting pull resistance will still be within the specified.

MMC1_SDCD
Add 100R series resistor
SDCD IO connected to ground directly when SD card is inserted

SD card connector
Verify need for separation between gnd and shield

U14 ESD device
Add filter cap
Follow U15

Regards,

Sreenivasa

Hello Surender Sharma

Added comments up to page 17

Please clarify if you want to use 

Partial IO mode 

Is the FT4232 (page 18) used for debug for the initial board or Wakeup from deep sleep

Page 13
EPHY supplies capacitors
1 uF cap 0201 used
Increase package size to 0402

CPSW_RGMII1_RESETn
PORz_OUT and RESETSTATz used
Use SOC IO instead or PORz_OUT to be able to perform local reset
Add provision to connect PORz_OUT or RESETSTATz
Configure for RESETSTATz

Page 14
RGMII TDx signals
Add series resistor provision 0Rnear to SOC MAC output TDx pins

delete R28 and c16 connected to SOC_CLKIN U6 buffer output
The components creates stub and is never expected to be used

Page 15
Bootmode supply
VCC3V3_XDS_TA is a single net
Change net name to SoC_DVDD3V3

Add external ESD protection for bootmode inputs in case the DIP switches are configured in an uncontrolled ESD environment

Boot mode resistors
Reduce pulldown R value to 47K

Pin 16
Place pulls near to the SOC JTAG pins
Follow Sk-AM62P-LP implementation
Refer pin connectivity requirements of the SOC data sheet

Page 17
Refer to AM62P for implementation of JTAG buffers and pulls
Buffers may be optional

Add external ESD protection provision
Mount when JTAG is used

Regards,

Sreenivasa

Hello Surender Sharma

Please use the below schematics for implementing the JTAG buffers with JTAG pulls placed near to the SOC JTAG signals

In case wakeup from deep sleep is required refer the below schematic for making updates to FT4232 section. If this section is used for debug you can ignore the same.  

 https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1332316/faq-am625-am623-custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am62b-p1-schematics 

Schematics with design updates made to the schematics

2185.PROC142B(002)_SCH_a.pdf

I am continuing to review the schematics.

Regards,

Sreenivasa

Kallikuppa Sreenivasa said:

MMC1_SDCD
Add 100R series resistor
SDCD IO connected to ground directly when SD card is inserted

I've added 100R resistor in series of MMC1_SDCD net, What about SDCD IO pins which are connect to U15.

Hello Surender Sharma

Thank you.

U15 is ESD diode connected in parallel. No connection change is required.

Regards,

Sreenivasa

Kallikuppa Sreenivasa said:

Please clarify if you want to use 

Partial IO mode 

Is the FT4232 (page 18) used for debug for the initial board or Wakeup from deep sleep

We are using FT4232 for initial development board, In production time , We will remove it.

Hello Surender Sharma

Thank you.

Are you considering using wakeup from CANUART (partial mode)

TCAN1043-Q1/SO-14 U9

I am not sure i understand the implementation.

VIO is the IO supply and this is connected to an SOC IO.

Regards,

Sreenivasa

Hello Surender Sharma

Could you please confirm the schematics you shared is partial or complete.

The clarification helps in review.

Regards,

Sreenivasa

Sir, as per my understanding, the schematic is complete. However, if I have missed or removed any section that is essential for the SoC functionality, kindly let me know.

Based on your suggestions, I have noted the required points and will implement all the changes together.

Kindly share the remaining page comments as well, so that I can update everything together and share the revised schematic once again. I hope that in the updated version, It will be free from error.

Hello Surender Sharma

Thank you.

Do you plan to implement wakeup from CANUART ?

The off-page connections shows page 33 and page 43.

I cant trace the CAN_FD_WKUP_SW_INH net.

I will try to provide the comments by Monday.

Regards,

Sreenivasa

Hello Surender Sharma

I added the review comments from 13..20 pages.

There were some updates on page 13..17 and i labelled them as New.

Page 13
EPHY supplies capacitors
1 uF cap 0201 used
Increase package size to 0402

CPSW_RGMII1_RESETn
PORz_OUT and RESETSTATz used
Use SOC IO instead or PORz_OUT to be able to perform local reset
Add provision to connect PORz_OUT or RESETSTATz
Configure for RESETSTATz

New
Enable the 2.2K pullup near EPHY MDIO pin

Page 14
RGMII TDx signals
Add series resistor provision 0Rnear to SOC MAC output TDx pins

delete R28 and c16 connected to SOC_CLKIN U6 buffer output
The components creates stub and is never expected to be used

Page 15
Bootmode supply
VCC3V3_XDS_TA is a single net
Change net name to SoC_DVDD3V3

Add external ESD protection for bootmode inputs in case the DIP switches are configured in an uncontrolled ESD environment

Boot mode resistors
Reduce pulldown R value to 47K

New
OK to use standard tolerance resistor for the bootmode configuration resistors

Pin 16
Place pulls near to the SOC JTAG pins
Follow Sk-AM62P-LP implementation
Refer pin connectivity requirements of the SOC data sheet

Page 17
Refer to AM62P for implementation of JTAG buffers and pulls
Buffers may be optional

Add external ESD protection provision
Mount when JTAG is used

Page 18
U83
MCU_UART
Level transistor connecting MCU_
Connect to VCC_3V3_MAIN in case wakeup from UART is required to be implemented

U35 ESD device
Add filter cap

1% tolerance used
Use standard tolerance 10K
Follow R513

SN74AVC4T245RSVR
Adjust the reference designators
Currently not visible

MCU_UART0_RTS_3V3
MCU_UART0_RX_3V3
Add a pullup
SOC IO buffers are off during and after reset

U91
WKUP_UART0
Connect to VCC_3V3_MAIN in case wakeup from UART is required to be implemented

FT4232 Reset
Add a parallel diode for dast discharge

Page 19
CAN_FD_WKUP_SW_INH
Source not visible
The offpage connection indicates page 43
please verify and update

WKUP_I2C0
A pullup is recommended for Open
drain output type I2C interfaces
irrespective of the IO configuration
Refer pin connectivity table of SOC
data sheet

WKUP_CLKOUT0
Add a TP
WKUP_CLKOUT0 is a buffered output of the high frequency oscillator (HFOSC0) 25MHz available during power-up as default

WKUP LFOSC0 has limited use case. Provide provision to ground Xi when not used

Add series resistor and parallel resistor in case you want to use 32K crystal plus oscillator
Refer SK schematics

Delete the PRU0 and VOUT0 net names for GPMC0..GPMC15
Name the nets as BOOTMODE0..BOOTMODE15
Connect bootmode configuration divider input directly to SOC bootmode inputs
FAQ reference
e2e.ti.com/.../faq-am625-am623-am644x-am243x-am62a-am62p-am62d-q1-am62l---bootmode-implementation-without-buffers

PRU_PRU0 1K series resistor can be deleted in case the signals are not used for alternate functions

SOC_VOUT0 signals series resistor can be deleted in case the signals are not used for alternate functions

Boormode input connection through 1K series resistor
Delete the 1K series resistor
Alternatively reduce series resistor to 22R

Page 20
MCU_I2C0
A pullup is required irrespective of IO usage or configuration
I2C interface not used
Open-drain output type buffer I2C interfaces have slew rate requirement when pulled to 3.3 V
An RC is recommended for slew rate control when I2C interface is used
Refer SK-AM62P-LP schematics

Providing provision for multiple clock option affects routing

Add series resistor for the UART interface signals near to the source for isolation or control of possible sigma; reflection

Regards,

Sreenivasa

Hello Surender Sharma

I added the review comments from 20.25 pages.

Page 20
MCU_I2C0
A pullup is required irrespective of IO usage or configuration
I2C interface not used
Open-drain output type buffer I2C interfaces have slew rate requirement when pulled to 3.3 V
An RC is recommended for slew rate control when I2C interface is used
Refer SK-AM62P-LP schematics

Providing provision for multiple clock option affects clock routing
implement the option that you would prefer
Using crystal is recommended

Add series resistor for the UART interface signals near to the source for isolation or control of possible signal reflection

Page 21

SoC_USB1_DRVVBUS
move 10K near to EN pin

add provision to bypass CMC using 0R
Refer SK-AM62P-LP schematics

Vbus divider optional for USB host

page 22

Add USB power switch controlled by USB_DRVVBUS to configure USB interface as host
add provision to bypass CMC using 0R
Refer SK-AM62P-LP schematics

USBC_CONN2_CC2
USBC_CONN2_CC1
Verify connection
Add provision for 5.1k pulldown and pullup to configure as host or device

Page 23
GPIO_OLDI_RSTn
Connect to SOC IO pin for local reset
Configure the software for the used IO

j22
Add a cap after the ferrite to minimize resonance
Move C379
Add 1 uF cap

Page 24
U97
verify the connection

CSI_VLDO_SEL
Connection not visible
Connect to an SOC IO pin
Configure the software based on the selected IO

IO_EXP_TEST_LED
Place pulldown near to pin 3 of FET
Connect to an SOC IO for indication of 3.3V presence
This is optional

Page 25
U5
add a bulk cap near to the oscillator supply pin

i2C0
I2C1
Note the I2C exception
add 47R series resistor to control the fall time

Open drain output type IO EXTINTn has slew rate limit specified when pulled to 3.3V supply.
Add an RC at the input.
Refer TMDS64EVM.

Add 22 pF glitch filter
This is for Improved EMC robustness

U10 MCU_PORz
Add 22 pF glitch filter
This is for Improved EMC robustness

Regards,

Sreenivasa

Hello Surender Sharma

I have provided the review comments for all the pages.

I will do one final review and share the schematics with the summary and the notes embedded to the PDF with our TI field team you are working.

Regards,

Sreenivasa

Hello Surender Sharma

Here are the issues i additionally observed based on the rereview for you to review as i do the final review and share the inputs.

U9
Not sure on the implementation
Checking if you are considering implementing CANUART wakeup
PMIC input supply needs to be controlled

U9
CAN_VIO_3.3V uC
Connected to SOC IO
This is the U9 IO power
Not sure if the IO can source the current
Connect to 3.3V SYS

CON1
Verify need for TVS protection for BAT input

U8
VCC_3v3_main is always on supply
Violated fail-safe operation
Connect to VCC_3V3_SYS (vddshv0)

U9
CMC2 bypass -Use 0402
Connect either CMC or resistor

U9 pin 3
In case wakeup fro CANUART is required,
Connect U9 supply to the always ON main supply VDDHV_CANUART

U10
Connect 5V supply to input B through a resistor
Follow wake connection

U9 pin 3
+5VALON should be +5V ALON

U7 input
+5VALON should be +5V ALON

U10 pin 1
+5VALON should be +5V ALON

U9 - pin9
+5VALON should be +5V ALON

U0-pin6
Connect an SOC IO and add required pulls
May be High

U9 - pin 14
Connect an SOC IO and add required pulls
May be pulldown

U9 pin 3
In case wakeup from CANUART is not used
Connect U9 supply to the always ON main supply 3.3V_VSYS

Regards,

Sreenivasa

Yes, We can use CAN wake-up, We are using TCAN1043 (Page 3), When any CAN message occur from vehicle then SoC get wake-up,  

I'm not understanding about the implementation of attached image.

Could you please clarify:

• Where should the CAN_FD_WKUP_SW_INH net be connected?

• Is this circuit required if we are already using the TCAN1043’s CAN message wake-up feature?

Kallikuppa Sreenivasa said:

Boot mode resistors
Reduce pulldown R value to 47K

Should the pull-up resistor value also be changed to 470 Ω to maintain the ratio?

Hello Surender Sharma,

470R is likely to draw more current. You could continue to have the 1.1K.

There is margin 

Regards,

Sreenivasa

Kallikuppa Sreenivasa said:

Page 18
U83
MCU_UART
Level transistor connecting MCU_
Connect to VCC_3V3_MAIN in case wakeup from UART is required to be implemented

Sir, Could you please clarify:

From my understanding, the SoC UART is connected to the FT4232 through a level shifter for debugging purposes.

Hello Surender,

I see this implementation on the schematics i am reviewing.

Can you please clarify the reference from where you reused in case this has been reused from a different reference schematics.

Surender Sharma said:

Yes, We can use CAN wake-up, We are using TCAN1043 (Page 3), When any CAN message occur from vehicle then SoC get wake-up,  

I'm not understanding about the implementation of attached image.

Could you please clarify:

• Where should the CAN_FD_WKUP_SW_INH net be connected?

• Is this circuit required if we are already using the TCAN1043’s CAN message wake-up feature?

Regards,

Sreenivasa

Hello Surender,Sharma, 

Please read the edited comment.

Surender Sharma said:

Page 18
U83
MCU_UART
Level transistor connecting MCU_
Connect to VCC_3V3_MAIN in case wakeup from UART is required to be implemented

Sir, Could you please clarify:

From my understanding, the SoC UART is connected to the FT4232 through a level shifter for debugging purposes.

Suggestion
U83
MCU_UART
Level transistor connecting MCU_UART0 ro SOC
Connect to VCC_3V3_MAIN in case wakeup from deep sleep using UART is required to be implemented
You can ignore the comment in case this is used for debug and not for deep sleep wakeup (based on our interaction 

Regards,

Sreenivasa

Kallikuppa Sreenivasa said:

U0-pin6
Connect an SOC IO and add required pulls
May be High

Sir, Please clear designator.

Hello Surender,Sharma, 

Please refer below:

U9-pin6

Connect an SOC IO and add required pulls

May be High

 Regards,

Sreenivasa

Hello Surender,Sharma, 

I have shared the PDF schematics with all the comments marked with the TI filed team.

You should receive the same any time.

Regards,

Sreenivasa

Ok Sir,

Thanks for review.

Hello Surender,Sharma, 

Regarding wakeup from CANUART (partial IO) please review SK-AM62-LP implementation.

A switch is used to simulate MCU_CAN1 wakeup

Regarding the MCU_CAN0 wakeup, follow the review comments and make the required updates.

Regards,

Sreenivasa

Hello Surender,Sharma, 

I assume the Field team shared the review comments summary and the PDF with comments embedded.

I assume you are making the updates.

Let me know if we can close the thread.

Do provide your feedback on the schematics review to the field team as required.

Regards,

Sreenivasa

Sir, we have received your review points from the field team and I will update all of them.

However, my query regarding the USB-C power supply is still pending. On page 22 (VBUS_TYPEC2 net), we are using this USB for booting purposes and I need a fixed applied voltage here. 

Hello Surender,Sharma, 

Thank you.

If you want to use the USB for boot, you are expected to configure the USB0 interface as device.

Regards,

Sreenivasa

Hello Surender,Sharma, 

Please refer Errata regarding the USB host (MSC) boot.

https://www.ti.com/lit/er/sprz487f/sprz487f.pdf

You might have to use the USB DFU (device) configuration.

Regards,

Sreenivasa

Sir,  

My query is only, What the fix voltage given to this USB.

We want to place a fix voltage LDO here for supply for this USB.

Hello Surender,Sharma, 

The switched voltage that connects to the USB host connector is +5V.

Regards,

Sreenivasa

Okay, Thanks,

+5V / 2A rated sufficient.

Hello Surender,Sharma, 

I dont know about the device you want to connect.

2A should be good to start with.

Please read the Errata regarding the issues with the USB MSC boot.

Regards,

Sreenivasa