Tool/software:
We are looking for a cost effective QSGMII Solution aiming to avoid an external Refclock Generator to connect one QSGMII Ethernet PHY.
In the Reference Manual i found Figure 12-1952 noting SERDES0_REFCLK as bidirectional Signals.
On the other hand there is the following thread in E2E discussing a Silicon errata preventing proper operation:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1491842/dra821u-pcie-refclock-sourced-by-processor/5729989?tisearch=e2e-sitesearch&keymatch=refclk%252520sourced%252520by%252520SOC#
Can you advise if i'ts feasible to integrate on QSGMII Phy without external refclock?
Many thanks and best regards
Stephan
