AM62L-PROCESSOR-SDK: tispl.bin doesn't work on the custom board.

Hi TO,

TO said:

1.Does tispl.bin work on DDR?

Yes, the TF-A provided in SDK 11.0.15.5 should have DDR4 support.

TO said:

1.Does tispl.bin work on DDR?

Yes, tispl.bin runs on DDR. If DDR is not configured properly, likely tispl.bin won't print any message on the console.

TO said:

3.If I change the DDR from EVM, I think I need to readjust the DDR parameters. Should I use the .dtsi file output by sysconfig with TF-A?

Yes, you should use SysConfig tool to generate the new DDR config data and integrate it to TF-A.

Hi Bin,

Thank you for your support.

Bin Liu said:

you should use SysConfig tool to generate the new DDR config data and integrate it to TF-A.

The DDR parameters have been adjusted and integrated into TF-A.
However, the console stopped at BL1 and could not proceed to BL31.

The console log is as follows:
Checking the log shows "bl1_platform_setup DDR init done" is output.
Does this mean that the DDR parameters are correct?
If the DDR parameters are incorrect and BL31 does not boot, how should I handle this?

NOTICE:  bl1_plat_arch_setup arch setup
NOTICE:  Booting Trusted Firmware
NOTICE:  BL1: v2.12.0(release):11.00.15-dirty
NOTICE:  BL1: Built : 12:24:23, May 29 2025
INFO:    BL1: RAM 0x7080b000 - 0x7080f000
INFO:    lpddr4_init <--
INFO:    lpddr4 dtb: ctl-data ptr=0x7080618c, pi-data=0x70806834, phy-data=0x70806da4
NOTICE:  BL1: dram_class: 10
INFO:    memory node =0x28
INFO:    lpddr4: probe done
INFO:    lpddr4/ddr4: init done
INFO:    start-status: offset =0x0
INFO:    start-status reg: before =0x10460a00
INFO:    Doing normal DDR initINFO:    lpddr4: Start DDR controller
INFO:    lpddr4: start completed successfully status=0x0
INFO:    start-status reg: after =0x10460a01
INFO:    LPDDR4 start completed !!
NOTICE:  lpddr4: post start - PI training status=0x29c02000
INFO:    lpddr4: post start - CTL Interrupt status=0x0
NOTICE:  bl1_platform_setup DDR init done
NOTICE:  k3_bl1_handoff ENTERING WFI - end of bl1
01000000011a0000616d36326c00000000000000544553540000010000000100

Hi TO,

TO said:

Checking the log shows "bl1_platform_setup DDR init done" is output.
Does this mean that the DDR parameters are correct?

The message only tells the DDR init is done, but it doesn't mean the DDR Config parameters are correct.

I am routing your thread to our DDR expert for comments.

The message means that the training completed, but it doesn't necessarily mean it completed successfully.

Can you send the DDR part number and/or datasheet, along with the changes you made from the tool (.syscfg file)

Regards,

James

Hi Bin and JJD,

Thank you for your support.

I will provide the following information about DDR4.
Could you please check if there are any issues with the DDR parameters?

* DDR part number 
   MT40A512M16TD-062EAIT:R

* datasheet and sysconfig file
   4863.DDR4.zip

There is one point of concern.
After analyzing the UART boot console log, the device type was TEST.
This has nothing to do with the issue of BL31 not being able to boot, right?

-----------------------
SoC ID Header Info:
-----------------------
NumBlocks            : [1]
-----------------------
SoC ID Public ROM Info:
-----------------------
SubBlockId           :
SubBlockSize         :
DeviceName           : am62l
DeviceType           : TEST
DMSC ROM Version     : [0, 1, 0, 0]
R5 ROM Version       : [0, 1, 0, 0]

for DDR config, lets start with just the basic changes, then optimize as needed.  Can you try to boot with the attached configuration:

/cfs-file/__key/communityserver-discussions-components-files/791/1563.k3_2D00_am62Lx_2D00_ddr_2D00_config.dtsi

/cfs-file/__key/communityserver-discussions-components-files/791/untitled-_2800_39_2900_.syscfg

which just changes density to 8Gb

Regards,

James

Hi JJD,

Thank you for checking and attaching the DDR parameters.

I confirmed the operation with the attached .dtsi file.

As a result, BL31 booted correctly. However, the startup of U-Boot failed.

Could you please tell me about the possible causes? The startup log is as follows.

NOTICE:  bl1_plat_arch_setup arch setup
NOTICE:  Booting Trusted Firmware
NOTICE:  BL1: v2.12.0(release):11.00.15-dirty
NOTICE:  BL1: Built : 12:24:23, May 29 2025
INFO:    BL1: RAM 0x7080b000 - 0x7080f000
INFO:    lpddr4_init <--
INFO:    lpddr4 dtb: ctl-data ptr=0x7080618c, pi-data=0x70806834, phy-data=0x70806da4
NOTICE:  BL1: dram_class: 10
INFO:    memory node =0x28
INFO:    lpddr4: probe done
INFO:    lpddr4/ddr4: init done
INFO:    start-status: offset =0x0
INFO:    start-status reg: before =0x10460a00
INFO:    Doing normal DDR initINFO:    lpddr4: Start DDR controller
INFO:    lpddr4: start completed successfully status=0x0
INFO:    start-status reg: after =0x10460a01
INFO:    LPDDR4 start completed !!
NOTICE:  lpddr4: post start - PI training status=0x29c02000
INFO:    lpddr4: post start - CTL Interrupt status=0x0
NOTICE:  bl1_platform_setup DDR init done
NOTICE:  k3_bl1_handoff ENTERING WFI - end of bl1
NOTICE:  BL31: v2.12.0(release):11.00.15-dirty
NOTICE:  BL31: Built : 12:24:23, May 29 2025
INFO:    GICv3 without legacy support detected.
INFO:    ARM GICv3 driver initialized in EL3
INFO:    Maximum SPI INTID supported: 991
ERROR:   Timeout waiting for boot notification
INFO:    stub copy 0x707f0000  0x80041000  0x707f6528
INFO:    A53 stub copy passed
ERROR:   Timeout waiting for receive
ERROR:   Message receive failed (-60)
ERROR:   Failed to get response (-60)
ERROR:   Transfer send failed (-60)
ERROR:   Unable to communicate with the control firmware (-60)
ERROR:   Failed to initialize SOC (-60)
INFO:    BL31: Initializing runtime services
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x82000000
INFO:    SPSR = 0x3c9
ERROR:   Agent 0 Protocol 0x10 Message 0x7: not supported

U-Boot SPL 2025.01-00464-g1d6ba4a32cdd-dirty (May 29 2025 - 19:36:32 +0000)
SPL initial stack usage: 1744 bytes
Trying to boot from MMC2
ERROR:   Agent 0 Protocol 0x10 Message 0x7: not supported


U-Boot 2025.01-00464-g1d6ba4a32cdd-dirty (May 29 2025 - 19:36:32 +0000)

SoC:   AM62LX SR1.0 TEST
Model: MY COMPANY MODEL
DRAM:  1 GiB
ERROR:   Agent 0 Protocol 0x10 Message 0x7: not supported
Core:  83 devices, 31 uclasses, devicetree: separate
NAND:  512 MiB
MMC:   mmc@fa10000: 0, mmc@fa00000: 1
Loading Environment from nowhere... OK
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
"Synchronous Abort" handler, esr 0x96000010, far 0x0
elr: 0000000084003254 lr : 0000000084003254 (reloc)
elr: 00000000bfe97254 lr : 00000000bfe97254
x0 : 0000000000000000 x1 : 00000000bffec000
x2 : 0000000000000065 x3 : 00000000bffadf98
x4 : 0000000000000000 x5 : 00000000bde863f0
x6 : 0000000000000021 x7 : 00000000bde8df60
x8 : 0000000000006bcc x9 : 00000000bde863e0
x10: 0000000000000000 x11: 00000000bde8b878
x12: 0000000000000000 x13: 0000000000000200
x14: 00000000bde667f0 x15: 00000000bde66688
x16: 00000000bfedc358 x17: 0000000000000000
x18: 00000000bde74df0 x19: 00000000bff7eb5e
x20: 00000000bff7eb38 x21: 0000000000000000
x22: 00000000bffa7b28 x23: 000000003be94000
x24: 0000000000000008 x25: 0000000000000000
x26: 0000000082039271 x27: 0000000082039000
x28: 0000000082039259 x29: 00000000bde66700

Code: b9002be0 79005be0 aa1403e0 9401daa7 (39400002)
Resetting CPU ...

resetting ...
INFO:    PSCI Power Domain Map:
INFO:      Domain Node : Level 2, parent_node 4294967295, State ON (0x0)
INFO:      Domain Node : Level 1, parent_node 0, State ON (0x0)
INFO:      CPU Node : MPID 0x0, parent_node 1, State ON (0x0)
INFO:      CPU Node : MPID 0xffffffffffffffff, parent_node 1, State OFF (0x2)

Best Regards,

TO