AM62L: MDIO level abnormal issue

Hello Zhang Pan,

Thank you for the query.

zhang pan said:

Our board has two phy DP83867IR mounted on the MDIO interface.

Can you please verify if unique address are configured.

zhang pan said:

At present, during the cold start test of the board, there is a situation where the mdio bus registration fails, as shown in the figure below. When the problem occurs, the clocks of MDIO and MDC are always in the following state, indicating that the MDIO level is obviously incorrect:

Can you confirm if the interface works some time and does not work some times or does not work any time?

Can you describe the waveform?

Do you have any capacitor load connected on the signals.

Regards,

Sreenivasa

It can be confirmed that the address is unique because it occasionally does not work, but most of the time it works normally。
The above image shows the waveforms measured on MDC (yellow) and MDIO (blue) when a problem occurred.

There is no capacitor load connected to the signal.

Hello Zhang Pan,

Thank you 

Can you please share the frequency of the occurrence - every 20 power cycles or 10 power cycles etc.

Is the issue seen on a specific board or on multiple boards?

Regards,

Sreenivasa

The reproduction cycle of this problem is irregular. Sometimes it takes 1000 power cycles to test, and sometimes it takes 200 power cycles to reproduce. Multiple boards have this issue, with some having a higher probability of reproduction and others having a lower probability. I noticed an issue with MDIO in Errata of AM62x Processor Silicon Revision 1.0, and I'm not sure if it's the same problem as on the current AM62LX.

Hello Zhang Pan,

Thank you 

https://www.ti.com/lit/er/sprz582a/sprz582a.pdf

Please refer errata. AM62L is not included for this erratum.

zhang pan said:

Sometimes it takes 1000 power cycles to test, and sometimes it takes 200 power cycles to reproduce.

Please describe the power cycle.

I assume the power architecture is based on TI PMIC.

zhang pan said:

The reproduction cycle of this problem is irregular. Sometimes it takes 1000 power cycles to test, and sometimes it takes 200 power cycles to reproduce. Multiple boards have this issue, with some having a higher probability of reproduction and others having a lower probability.

Do you have board that does not show this issue at-all.

Can you share the schematics for a quick check.

Regards,

Sreenivasa

1、power cycle:

We use a switch power supply to power the board, and the network port of the board is connected to a gigabit switch through a network cable. After the system is started, a detection script will be launched to check whether the network port can negotiate 1Gbps. If the detection is successful, the switch power supply will be powered off for 5 seconds and then powered on again for the next cycle. If the detection fails, a failure signal will be fed back to the switch power supply to stop cutting off power.

2、At present, some boards have been tested for over 10000 power cycles without encountering this issue.

3、We have sent the schematic diagram to your email.

Hello Zhang Pan,

Thank you for the inputs and schematics.

Based on a quick check i do not find any obvious issue.

To isolate the issues below are the 2 suggestions

The MDIO from the SOC is going to EPHY1 and WPHY2 through separate series resistors 

Would you be able to isolate one of the EPHY and test on only 1 EPHY 

Can you add a series resistor 500R instead of 0R and test. When you see the issue please measure the signals on both sides of the resistor.

Can you change the ETH1 PHY address from 0 to another address. EPHY2 had 0001 address.

Can you please confirm the switching frequency.

The recommendation is to ensure all the SOC voltages decay to below 300mV before the next power cycle starts.

Regards,

Sreenivasa

Hello Zhang Pan,

Did you have a chance to test with above conditions and have some observations.

Regards,

Sreenivasa

Thank you for your suggestion. We are currently testing according to your suggestion.

Hello Zhang Pan,

Thank you, please update when you have some results.

Regards,

Sreenivasa

Hello Zhang Pan,

Checking if you made some progress?

Regards,

Sreenivasa

Hello Zhang Pan,

Checking if you made some progress?

Regards,

Sreenivasa

Thank you for your attention. Our current situation is as follows:
I found a board that is easy to reproduce the problem, and this board can reproduce the problem within 100 cycles. The PHY ADDR of this board was changed from 0 to 2, and only reproduced twice. After that, this board was never reproduced again (approximately 7500 cycles did not reproduce).
I changed the PHY ADDR of this board from 2 to 0 again, and the probability of reproduction decreased after long-term testing (previously it could be reproduced within 100 cycles).
From the current test results, changing PHY-ADDR from 0 to 2 does not solve this problem.
We have now added a hardware reset for phy in the driver and are currently undergoing long-term testing.

Hello Zhang Pan,

Please update the thread when you have additional results.

Regards,

Sreenivasa