Looking at the AM1802 errata (Literature Number: SPRZ340C) where, at advisory 2.1.7, the mechanism of a current leakage between 3.3V rail and 1.8V rail is explained. I want to design a circuit to go around this and I have some questions.
- On the graphs and text explanations appear a Vt but the voltage range is not specified. Could you give some numbers for it?
- The maximum current leakage is 140mA for all I/O powered at 3.3V. Could I assume a lower fault current if only bank A is powered at 3.3V ?