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TDA4VH-Q1: PCIe Traffic Class programming

JPH-FR
Intellectual 271 points
Part Number: TDA4VH-Q1


Tool/software:

Hi,

 

In order to output a PCIe with a given Traffic Class (TC) the mechanism seems to be one described in TRM §12.2.3.3.7.2.1 PCIe Outbound Address Translation Bypass, where the TLP parameters come from a PCIE_CORE_VMAP_MMRS_EXT_desc_j register.

 

But the post TDA4VH-Q1: PCIe Traffic Class setting - Processors forum - Processors - TI E2E support forums (near the last contribution), says that bypassing address translation, historically, has been unsupported in the SDK.

 

Does this means that fixing TC of an outbound TLP is not supported by the SDK ?

If not supported, is there another method to fix TC ?

 

Thanks,

 

JPH

  • 0
    TI__Guru 55073 points

    Hi JPH,

    No good support in our SDK unfortunately. Would you mind me asking, what is the end goal? Are these series of questions for a custom OS development, or support for a new PCIe device under Linux, or something else?

    Regards,

    Takuma

  • 0 in reply to Takuma Fujiwara
    Intellectual 271 points

    Hi Takuma,

    These series of questions is related to the design of a PCIe communication network between C7x cores of several Jaicnto SOCs in which some messages need a greater priority than others.

    May I assume that the feature I am interested in (setting the priority of messages on a PCIe network), even if it is not supported by the SDK, has been tested by TI and works, and that I should be able to implement it successfully, even if it requires effort? Or should I assume that it is not available?"

    Thanks for your support,

    JPH

  • +1 in reply to JPH-FR
    TI__Guru 55073 points

    Hi JPH,

    Internally, there was a SDK requirement in the Jira system for Linux PCIe driver to program QoS parameters such as VC/TC back in 2021. It was not linked to any customer requirement, and lacking customer usecase, so the feature had been deprioritized.

    So, there is no example or testing internally at TI for the QoS feature of PCIe. All traffic is sent at same priority.

    Regards,

    Takuma