• State
  • Replies 4 replies
  • Subscribers 100 subscribers
  • Views 112 views
  • Users 0 members are here
Support feedback
Options
Options
Related

TDA4VE-Q1: LPDDR4 design guide what the exact value for the pull up res of ODT?

Biao Li
Expert 6470 points
Part Number: TDA4VE-Q1
Other Parts Discussed in Thread: AM62P

Tool/software:

Hi Expert,

From below guide, I can see the resistor value for others, but there is missing the value of ODT_CA_A/B, do we have any recommend value? In EVM, we are using 10K, but I want to double check about this, is it the best value? because from the Sitara AM62P board, we use 2.2K, and some customer is using 1K, so I want to figure it out, what is the best value? can you share some standard (Memory datasheet or JEDC?) customer need to follow, or any pull up resistor value can be accepted?

Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F)

BR,

Biao

  • 0
    TI__Guru 52525 points

    The specific resistor value is not critical - as its not a calibration or termination resistor value.  It is a logic input - so any resistor value can be used as long as it sets the correct logic value. All the resistor values you mentioned (10K, 2.2K, 1K) should all be fine.

  • 0 in reply to Robert Eschler
    TI__Expert 6470 points

    Hi Robert,

    So if this signal is connected to 1.1v, the pull up resistor value is not matter, right? but previously in TDA4VEN EVM, customer connect to 0.55v(pull up to 1.1v with 10K and pull down with 10K), the DDR will have some stability issue (can work in low frequency, but failed in high frequency), and Micron lpddr4 can work in all frequecy, but Samsung and other ddr vendor can't work. this is interesting result if this is just logic input. capture from the micron ddr datasheet, can it be applied to all DDR vendor?

     

    BR,

    Biao 

  • 0 in reply to Biao Li
    TI__Guru 52525 points

    The signal is an input and the responsibility of the board design is to provide the proper logic high or logic low value.  The mentioned 0.55V was an error because that is an invalid logic level.  That voltage resulted from an on-board pull-up and on-board pull-down....which is a manufacturing mistake and not a valid implementation.  There should be no pull-down resistor on board. 

    The 'weak' internal pull-down resistor and/or leakage current into the input pin may vary across memory manufacturers - so I recommended customer references those datasheets.  (For example - in datasheet I am reviewing, I see no definition of weak internal pull-down, but I do see max input leakage of 4uA).  In general - resistors in range of 1K to 10K should have no issue setting proper logic level for this pin. 

  • 0 in reply to Robert Eschler
    TI__Expert 6470 points

    Hi Robert, 

    Thanks for the detail explanation, let me double check with Samsung team about this pull up value recommendation, I can't see the detail description in Samsung datasheet as well.

    Robert Eschler said:
    The 'weak' internal pull-down resistor and/or leakage current into the input pin may vary across memory manufacturers

    due to the weak pull down, may be smaller pull up resistor will be better, right? but I can't make it clear only from the LPDDR4 datasheet, form below bloack diagram, the internal pull down may not have any impact to the ODT_CA because of the RCVRS (not sure what it is). I will let customer try smaller pull up value to have a try first. Thanks a lot for your support.

    BR,

    Biao