AM6442: QSPI DAC mode

Biao Li

Part Number: AM6442

Tool/software:

Hi Expert,

customer is using VxWorks os, and they want to enable the DAC mode, but they find some mismatch between the input and output, they have some debug as below:

This problem we take data analysis, is while writing flash, although we wait for the ospi _cfg (0x0) register bit31 bit bus to be idle, but the actual data is not sent out. Then another packet comes in, sending 50 cm clear. So does this bit of such a bus idle really mean that the data is sent? Are there any other status bits to indicate? To make sure that my data is sent on the next shot.

Can you help answer customer question?

BR,

Biao

4 months ago

0 Vaibhav Kumar 4 months ago

TI__Guru 51007 points

Hi Biao,

I see write operation being talked about for DAC mode.

Just to clarify, for QSPI NOR Flash and NOR Flash in general we currently support INDAC writes and DAC reads.

Thanks,

Vaibhav

0 Biao Li 3 months ago in reply to Vaibhav Kumar

TI__Expert 6610 points

Hi Vaibhav,

Customer is using idac mode to write 512 bytes of data in total, norflash calls xfer twice, the first 256 bytes through the logic analyzer saw the data transfer normally, However, the second 256-byte transmission, the bus has no pull tab and no data, resulting in the wait for the idac read and write completion interface timeout write failure, have you encountered this situation? Is there a problem with the registry configuration of our qspi after the first 256-byte write is complete? can you share some example code to customer how to use idac mode?

can you help also loop Linux/uboot expert in to share some example code to customer?

BR,

Biao

0 Vaibhav Kumar 3 months ago in reply to Biao Li

TI__Guru 51007 points

Hi Bio,

Biao Li said:
can you help also loop Linux/uboot expert in to share some example code to customer?

I am familiar with MCU+ SDK driver for INDAC writes. If you need a reference to the same, here you go:

Driver Implementation of the INDAC writes: https://github.com/TexasInstruments/mcupsdk-core/blob/next/source/drivers/ospi/v0/lld/ospi_v0_lld.c#L1558
Example to demonstrate INDAC writes: https://github.com/TexasInstruments/mcupsdk-core/blob/next/examples/drivers/ospi/ospi_flash_io/ospi_flash_io.c
Note: By default in the above example, DAC reads and INDAC writes are performed for NOR Flash on the TI EVM.

For Linux/uboot query, I will loop in the correct expert.

Regards,

Vaibhav

0 Vaibhav Kumar 3 months ago in reply to Biao Li

TI__Guru 51007 points

Also clarify the term which you wrote above as "idac". Did you meant to write DAC or INDAC?

0 Paula Carrillo 3 months ago in reply to Vaibhav Kumar

TI__Mastermind 40580 points

Hi, for linux driver example you can check: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/spi/spi-cadence-quadspi.c?h=ti-linux-6.12.y-cicd

Basically, DAC and INDAC are possible. Currently cadence driver automatically selects between DAC/INDAC.

In driver initialization DAC is enabled. https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/spi/spi-cadence-quadspi.c?h=ti-linux-6.12.y-cicd#n3592

For read operations depending on the size (or if direct mode is disabled) it could be DAC or INDAC. https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/spi/spi-cadence-quadspi.c?h=ti-linux-6.12.y-cicd#n3050

For writing it is similar, depending on the size, if direct mode is enabled/disable, and if DTR is enabled then we can have DAC (memcpy) or INDAC. https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/spi/spi-cadence-quadspi.c?h=ti-linux-6.12.y-cicd#n2817

Hope this helps,

Paula

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AM6442: QSPI DAC mode