AM6442: TCM access

Hello Holger,

On the AM243x/AM64x R5F Subsystem:

• Each R5F core has private TCM (64 KB per core).

• TCM is tightly coupled to the CPU for performance.

• Each core can access any core’s TCM via its SOC address space through the SoC interconnect.

Proposed Method

1. Allocate TCM for Core0

• Core0 reserves a portion of its TCM for a shared data buffer.

2. Notify Core1 via IPC

• Core0 sends an IPC message to Core1 once data is ready.

• This ensures proper synchronization, preventing Core1 from reading incomplete data.

3. Core1 Reads via Global Address Space (Mapped Through SoC)

• Core1 accesses Core0’s TCM buffer using its SOC address space, which maps to the same physical memory via the SoC interconnect.

Regards,

Anil.

Hi Anil,
Does TCM performance decrease if both CPUs access the TCM at the same time? How is access regulated?
Do you know if there is some app note?

Best regards, Holger

Hello Holger,

Core1 always accesses Core0 TCM through the SoC global address space and not through the local R5F memory view.

Due to this, Core1 observes higher access latency when reading Core0 TCM compared to Core0’s local TCM access.

When Core0 and Core1 access Core0 TCM simultaneously, Core1 takes more time because its access is routed through the SoC interconnect, whereas

Core0 uses the local TCM path.

Regards,

Anil.