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AM6421: SRAM, DCACHE and ICACHE -> Software Access Question

Darren Coste
Prodigy 40 points
Part Number: AM6421

Tool/software:

The datasheet mentions 2MB of on-chip SRAM.
Memory Map from the TRM shows this is mapped from 0x070000000 ~ and is useable.

However, I noticed each R5F core also has 8MB of ICACHE / 8MB of DCACHE in the mappable regions.
I am not familiar with memory mapping - on a learning curve.

However I was wondering, can say 2MB be set aside by software so that you could access (r/w) it freely?
Like how you would map data to SRAM in a program?

I am considering this in a baremetal implementation - no linux. Just want to know if you can make a C program that grabs control of some of this cache space.

From the SDK:

https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/latest/exports/docs/api_guide_am243x/KERNEL_DPL_CACHE_PAGE.html

Mentions API for ICACHE and DCACHE but not sure where to go from here...

  • 0
    Prodigy 40 points

    The Arm Cortex-R5 Technical Specifications overview (https://developer.arm.com/Processors/Cortex-R5) states the following about ICACHE, DCACHE and TCM:

    Cache controllers Harvard memory architecture with optional integrated Instruction and Data cache controllers. Cache sizes are in-dependably configurable from 4 to 64KB. Cache lines are either write-back or write-through.
    Tightly-Coupled Memories Optional Tightly-Coupled Memory interfaces are used for highly deterministic or low-latency applications that may not respond well to caching ( e.g. instruction code for interrupt service routines and data that requires intense processing). One or two logical TCMs, A and B, can be used for any mix of code and data. TCM size can be up to 8MB. TCM B has two physical ports, B0 and B1, for interleaving incoming DMA data streams.

    This seems to indicate I/D caches have a limit of 64KB while ATCM/BTCM can be setup for 0 ~ 8MB.

    The TRM of AM243x / AM64x seemed to indicate allocation of 8MB for ICACHE / DCACHE. 

    The point of all my questions is this: Is there some way to set aside 2MB of any kind of internal cache for use in storing data controlled by a program?

  • +1 in reply to Darren Coste
    TI__Mastermind 46806 points

    Hello Darren Coste,

    ICACHE / DCACHE :

    • Caches cannot be “reserved” as RAM”.
    • They are hardware-managed buffers for instructions (ICACHE) or data (DCACHE).
    • Accessing them directly as normal memory is not supported — the CPU sees them only through the cache controller.
    • On the Cortex-R5: ICACHE and DCACHE can be up to 64 KB each per core, not 8 MB.  iThe TRM likely shows the addressable region, not actual physical cache size.
    • You cannot safely use the cache as scratch memory for general-purpose data.

    Regards,

    Anil.

  • +1 in reply to Darren Coste
    Mastermind 7460 points

    That 8MB ranges in the memory map are part of the R5f AXI slave interface, i.e. they allow access to the R5f's cache e.g. from another R5f or from the A53. The R5f TRM has a chapter on the "Memory map when accessing the cache RAMs", which explains why the region is 8MB (23 bits used for decoding).

    In a baremetal application you would be able to use most of the 2MB internal SRAM (MSRAM @ 0x70000000). The last part of that MSRAM is reserved for SysFW. When loading your application via SBL you need to be aware that SBL also runs from that MSRAM, as this limits where you can link your application. At runtime the SBL memory is available. There could be other users of the MSRAM, e.g. if you want to use the ICSSG ethernet.

    Accesses to the MSRAM have a considerably higher latency than TCM, so if you have performance critical code you might want to put that into TCM. The R5f caches can cache accesses to MSRAM, which helps to cope with this latency.

    Regards,

    Dominic