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DRA78XEVM: Unexpected stall cycles in tracing

Salvatore Lionetti
Prodigy 100 points
Part Number: DRA78XEVM

Tool/software:

Hi,

on C66, CCS 10, I'm tracing a simple function that do some checks and when these checks are positive invoke a function derived from an address parameter, I see the instruction

BNOP.S2 B3,4 

Taking 4 cycles (row 9, column Delta cycles) as expected

but then the same address is showed again with 8+1 delta cycles.

This is not expected, as reported on sprugh7:

Why are these extra cycles reported? Are just a tool artifact?

The trace option is "Custom Core Trace", with Trigger1 "Start trace" at "Point", Trigger2 "Stop trace" at Point.

Thanks for the attention

  • 0
    TI__Mastermind 32265 points

    Salvatore,

    I believe this is a symptom from the Pipeline stall, due to some hazard, "bubbles" or cycles are inserted delaying the entire pipeline including the BNOP, causing it to be processed for extra cycles as it waits its turn. then a second one is called again and can branch already and the BNOP is terminated in only one cycle.. example from same sprugh7:

    Best,

    Josue

  • 0 in reply to Josue Zamitiz-Ayala
    Prodigy 100 points

    Thanks, the problem is that if the stall is not accounted on the intended instruction it is hard to understand the situation.

    In this sense, do you know why only for some pipeline stall appears "Execution Continued"?

  • 0 in reply to Salvatore Lionetti
    TI__Mastermind 32265 points

    Salvatore,

    I am not 100% sure, (not a C66 architecture expert), but it seems like it is a stall the the processor is able to deal with and this is the signal that it resumes its normal pipelined operation. Other stalls might not be as easily recoverable and should show more details.

    -Josue

  • 0 in reply to Josue Zamitiz-Ayala
    Prodigy 100 points

    Josue, thanks for your response. Do you think is there a "C66 expert" that can give a look into this? Thanks

  • 0 in reply to Salvatore Lionetti
    TI__Mastermind 32265 points

    Salvatore,

    Unfortunately this is a gap in our support so we no longer have a dedicated C66 expert. These parts are legacy so there has been some attrition over the years. 

    Some of your questions are answered in the document sprugh7, like for example:

    this part explains your initial question, or as I explained the bubbles, as it was taught to me from fundamental computer architecture.

    My analysis is an inference from the  TMS320C66x DSP CPU and Instruction Set Reference Guide when referring to branch instructions, See Chapter 8.14

    Please read this document in its entirety for better clarity of C66 instructions and programming model.

    -Josue