66AK2H14: Tx driver equalization

Hi,

The assigned engineer is out of office today. Expect response early next week.

Thanks,
Keerthy

Hi Bruno,

Apologies for the delay and Thanks for the patience.

As mentioned in KeyStone II Architecture Serializer/Deserializer (SerDes) - User Guide, the transmitter utilizes a 4-tap FIR filter with coefficients Cm, C₀, C₁, and C₂.

Then the output can be expressed as: 

y(n) = Cm⋅dn+1​+C0​⋅dn​+C1​⋅dn−1​+C2​⋅dn−2

The coefficients Cm, C₀, C₁, and C₂ can be positive or negative, based on the lane control register bits.

And the normalization condition here is as follows:

(Normalization Eq:1 - Generic Mode) ∣Cm∣+∣C0​∣+∣C1​∣+∣C2​∣=1

As the values of Cm, C₁, or C₂ are increased, C₀ is automatically decreased to maintain this equality.

from the above screenshot, it is mentioned that "The equalization ratios implemented by the transmitter can be calculated from the PCIe tap-coefficients in PCIe mode or register settings in generic mode."

In PCIe mode, the SerDes usually supports post-cursor de-emphasis (C1) and main cursor (CM). In those modes, The C2  (pre-cursor tap) effectively not utilized /is set to zero.

Therefore, the normalization simplifies to:

Cm + C0 + C1 = 1 ( Eq:2 - PCIe equalization case, where only Cm and C1 are relevant.)

In Section 14.2.2 : " PCIe mode, TX driver equalization and swing/slew settings are controlled by a Look-Up table (LUT). For any reason, if these setting need to be controlled through registers then the override enable must be asserted"

Regards,

Betsy Varughese

Thank you Betsy for your answer.

Sorry, I did not mention that my application was not PCIe but 10G-XFI.

Therefore I did not really consider the 14.2.2 § which do focus on PCIe

therefore it was not obvious that the calculation example chosen in § 14.2.3 (which I consider as a generic explanation) was actually oriented to PCie.

Then for 10G you confirmed that C2 was involved in the  TX waveform (at the condition that override is asserted).

Is this correct ?

with best regards,

Bruno

Hi Bruno,

Could you please go through the document https://www.ti.com/lit/an/sprac37/sprac37.pdf?, I believe it will be helpful in addressing this query.

Regards,

Betsy Varughese

Hi Betsy,

Can you explain how the Override can be achieved?

The spruho3a (last version from July 2016)  table 14-2 says that OVR controls can be found at address LANE_0A8, LANE_0A0

but these address do not exist 

Can you precise please ?

regards,

BRuno

Hi Bruno, 

I don't think its a CPU memory mapped address, Instead It is the offset inside the SerDes lane register space. 

You can find the memory map details in Chapter 16 of https://www.ti.com/lit/ug/spruho3a/spruho3a.pdf?.

Regards,

Betsy Varughese

Hi Betsy,

I am not sure to understand your comment.

I was precisely referring to the spruho3a document ! and precisely the Serdes lane register space.

LANE_0A0 and LANE_0A8 are defined as "reserved"

Hi Bruno,

Bruno B said:

LANE_0A0 and LANE_0A8 are defined as "reserved"

Could you please check this? , For PHY-A, those lane's are not reserved.

Yes, If you are working with PHY-B, in that case the configuration is “reversed.”

Regards,

Betsy Varughese

Hi Betsy,

It seems that your picture corresponds to PHY-A serdes mapping (table 16-1)

For 10G which is our use case we have to look at PHY-B table (see my previous snapshot extracted from table 16-2)

Don't you agree ?

Regards,

Bruno

Hi Bruno,

Yes I have updated the comment. 

Bruno B said:

The spruho3a (last version from July 2016)  table 14-2 says that OVR controls can be found at address LANE_0A8, LANE_0A0

This table actually describes about the "Register Descriptions for PCIe Mode TX Driver Slew, Equalization and Amplitude Settings".

For Generic Mode, Please refer the below table.

& Table 14-4. details about the "TX Driver Register Signals for PHY-B".

Regards,

Betsy Varughese