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PROCESSOR-SDK-J784S4: Set UART Baud Rate to a Bigger Value Than 3.6 Mbps

Gokhan Ugurel
Prodigy 85 points
Part Number: PROCESSOR-SDK-J784S4

Tool/software:

Platform: J784S4XG01EVM

SDK: ti-processor-sdk-rtos-j784s4-evm-11_00_00_06

Core: R5F

OS: FreeRTOS

Run With Linux: Yes

Image: Yocto build with processor-sdk-analytics-11.00.00-config.txt file

Request:

Need to increase UART baud rate to a bigger value than 3.6 Mbps for R5F cores. Is there a way to change clock frequency for UARTs?

Information:

  • When i review 1.2.21 Universal Asynchronous Receiver/Transmitter Section in spruj52d TRM document for J784S4 platform, i see that the maximum baud rate for UART peripherals is 3.6 Mbps for 48 Mhz clock.

"Baud rates up to 3.6 Mbps with 48 MHz functional clock"

  • I can not find a UART register like in AM57 cores that we can change the clock as 192 Mhz and increase the baud rate to 12 Mbps (setting FUNC_192M_CLK in CM_L4PER_UARTx_CLKCTRL registers) in J784S4 TRM document.

  • 0
    TI__Genius 11810 points

    Hi Gokhan,

    I have requested the corresponding to expert to have a look into this query. Thanks in advance for your patience.

    Regards

    Gokul

  • 0
    TI__Expert 4960 points

    Hi Gokhan,

    In the TRM registers file, can you please search for USART_CLKSEL? This is a mux which controls the corresponding USART FCLK. For example, MCU_USART0 has a register named CTRL_MMR_CFG0_MCU_USART_CLKSEL:

    MCU_USART0 FCLK selection

    • 1'b0 - MCU_PLL1_HSDIV3_CLKOUT (48kHz)
    • 1'b1 - MAIN_PLL1_HSDIV5_CLKOUT (192MHz)

    Regards,
    Mark

  • 0 in reply to Mark L.
    Prodigy 85 points

    Hi Mark,

    According to the TRM document that i am currently using (SPRUJ52D – JUNE 2022 – REVISED JULY 2024, link),

    I can only validate 2 CLKSEL signals;

    - WKUP_PER_CLKSEL (Table 5-35, Page 302) for WKUP_UART_0. Values are [19.2, 20, 24, 25, 26, 27] MHz

    - MCU_USART_CLKSEL (Table 5-35, Page 339) for MAIN_UART_10 (which is an MCU UART i think, even if the name is MAIN. When i check page 298, MCU_PLL_1.HSDIVOUT3_CLK is the default clock for WKUP_I2C_0, MCU_DCC_0, MCU_I2C_0, MCU_I2C_1, MAIN_UART_10 by default.)

    In page 299, MAIN_SYSCLK0 is the clock for all other UARTs and as far as i understand, this clock can not be changed by a mux or something like that. There is no reference for 48 MHz or 192 MHz inside the document. We plan to use Main Domain UARTs at a higher baud rate than 3.6 Mbps.

  • +1 in reply to Gokhan Ugurel
    TI__Expert 4960 points

    Hi Gokhan,

    For Main Domain UARTs, can you please search for CTRL_MMR_CFG0_USARTn_CLK_CTRL, where n=[0,9].

    To set USART FCLK to 192MHz, please set the divider to /1, which is equivalent to setting bitfield [1:0] to 2'b0.

  • 0 in reply to Mark L.
    Prodigy 85 points

    Hi Mark,

    Everything is clear now.

    Thanks