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TDA4VM: TDA4

jagadeesh Kanade
Prodigy 30 points
Part Number: TDA4VM

Tool/software:

WE are not able to C7x Optimized code on TDA4 emulator. If information on how to execute on TDA4 please suggest

  • 0
    Prodigy 30 points

    WE are not able to run C7x Optimized code on TDA4 emulator. If information on how to execute on TDA4 please suggest

  • 0
    Prodigy 90 points

    Hi TI team,

    We have developed an image processing algorithm using c7x tool chain ( ti-cgt-c7000_4.1.0.LTS ) and we compiled it using cl7x compiler. 

    Did this using the code composer studio tool (version 12.4) in ubuntu system (version 22). Thereafter we followed the CCS set up for j721e Soc and got connected to the Cores in the Soc using XDS110 on board debugger via UART connection. And When we tried to load the .out on the c7x core we have faced a memory mapping issue. Can you please help us loading the .out on the C7x core ?

    Error displayed in Cosole after trying to load the .out :


    C71X_0: File Loader: Verification failed: Values at address 0x0000000000008030 do not match Please verify target memory and memory map.
    C71X_0: GEL: File: /home/srinivasthalam/workspace_v_latest/rgbir_instrinsic/Debug/rgbir_instrinsic.out: a data verification error occurred, file load failed.

  • 0 in reply to Srinivas Thalam
    TI__Intellectual 1920 points

    Hi,

    Could you please confirm if you followed these steps to set up CCS? https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/psdk_rtos/docs/user_guide/ccs_setup_j721e.html

    I am also sharing an FAQ with you on how to perform target configuration and test the connection in CCS: [FAQ] TDA4VL-Q1: How to create "Target configuration" and do "Test connection" on J721S2 EVM


    You can also refer the following document: software-dl.ti.com/.../troubleshooting-data_verification_errors.html

    Srinivas Thalam said:
    Thereafter we followed the CCS set up for j721e Soc and got connected to the Cores in the Soc using XDS110 on board debugger via UART connection

    Could you please confirm if you are trying to run the .out file in bare-metal using NO BOOT mode? If so, please try connecting through the XDS110 JTAG interface.
    Could you please share the .out file you used so that I can test it on my end? Also, kindly verify the path of the GEL file you used.

    Regards,
    Shabary S Sundar

  • 0 in reply to Shabary S Sundar
    Prodigy 90 points

    Hi Shabary,

    1. Yes we have followed the exact set up you mentioned.
        https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/psdk_rtos/docs/user_guide/ccs_setup_j721e.html

    2. .ccxml file also created as you mentioned.

         e2e.ti.com/.../faq-tda4vl-q1-how-to-create-target-configuration-and-do-test-connection-on-j721s2-evm

    3. NO-boot is also set

         SW8[1-8] = 1000 1000  &   SW9[1-8] = 0111 0000

        Yes, we have connected j3 usb connector only (ubuntu pc -> j3 ).

    4. Since we have followed everything as mentioned in TI documentation and faced the issue,

        I have created a reference document for your better understanding the issue and attaching it here. 
        Please go through this document and let us know if .out needed, meanwhile we will go through the error reference link you have shared. 

        ccs setup documentation link.

    5. We will share you a sample .out in a short.


    Regards,
    Srinivas Thalam

  • 0 in reply to Srinivas Thalam
    TI__Intellectual 1920 points

    Hi,

    Srinivas Thalam said:
    Please go through this document and let us know if .out needed, meanwhile we will go through the error reference link you have shared.

    I was unable to access the documentation link you shared. Could you please check if it is accessible externally?

    Regards,
    Shabary S Sundar

  • 0 in reply to Shabary S Sundar
    Prodigy 90 points

    Okay I am sharing the link from my personal drive, please try this.
    Sendig you in mail also.



    https://drive.google.com/file/d/1yvH4mt5b5SAzhJeEEZqQsJCQ2DgPR2qw/view?usp=drivesdk

  • 0 in reply to Srinivas Thalam
    TI__Intellectual 1920 points

    Hi,
    You can mail me these documents.(x1246483@ti.com)

    Regards,
    Shabary S Sundar

  • 0 in reply to Srinivas Thalam
    TI__Intellectual 1920 points

    Hi,
    Have you tried running any sample .out file for the C7x? Did it work with the same setup? Also, are you working on Linux or Windows OS?

    Regards,
    Shabary S Sundar

  • 0 in reply to Shabary S Sundar
    Prodigy 90 points

    Hi,

    Hope you have received the document I sent in mail.
    I have tried the sample .out also earlier but still faced the same error loading the file. I am working on Ubuntu 22.


    Regards,
    Srinivas Thalam

  • 0 in reply to Srinivas Thalam
    TI__Intellectual 1920 points

    Hi,

    Below I have attached (share via mail) a sample .out for your reference. The executable is validated from our end on J721E and its working fine. Could please check and confirm the same from you end?

    [MCU_Cortex_R5_0]  SCICLIENT_CCS_INIT: Apr 10 2025, 15:32:46Sciclient_Init Passed.
=================================================================
 DEVGRP = 1
=================================================================
SYSFW Common Board Configuration with Debug enabled... PASSED
SYSFW PM Board Configuration... PASSED
SYSFW Security Board Configuration... PASSED
=================================================================
Sciclient Dev Group 01 initilization started
Power on the WKUPMCU to MAIN and MAIN to WKUPMCU VDs... PASSED
=================================================================
 DEVGRP = 2
=================================================================
SYSFW Common Board Configuration with Debug enabled... PASSED
SYSFW PM Board Configuration... PASSED
SYSFW Security Board Configuration... PASSED
=================================================================
 DMSC Firmware Version 11.0.9--v11.00.09+ (Fancy Rat)
 Firmware revision 0xb
 ABI revision 4.0
=================================================================
Sciclient_ccs_init Passed.
SCISERVER Board Configuration header population... PASSED
[C71X_0] DSPLIB debug DSPLIB_TEST_init - 67: rand seed = 1757418813
DSPLIB_DEBUGPRINT  DSPLIB_max_d CP 0
DSPLIB_DEBUGPRINT  DSPLIB_max_d CP 1
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
               DSPLIB_max testing starts.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| No  | ID  | Status | Num pt  | Kernel Init   | Kernel Compute  | NatC Compute  | Arch. Compute | Efficiency  | Est.  Compute | Accuracy    | Description
|     |     |        |         |  cyc          |  cyc            |  cyc          | cyc (est.)    | vs Arch.(%) | cyc (est.)    | vs Est.(%)  |            
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DSPLIB_DEBUGPRINT  DSPLIB_max_d data_type 12 dataSize 512 
DSPLIB_DEBUGPRINT  DSPLIB_max_d pIn1  64800380
DSPLIB_DEBUGPRINT  DSPLIB_max_d CP 0
DSPLIB_DEBUGPRINT  DSPLIB_max_d CP 1 status_init 0
Enter DSPLIB_max_init_checkParams
DSPLIB_DEBUGPRINT Enter DSPLIB_max_init
DSPLIB_DEBUGPRINT DSPLIB_max_init pKerPrivArgs->blockSize 512 bufParamsIn->data_type 12
DSPLIB_DEBUGPRINT bufParamsIn->data_type == DSPLIB_FLOAT32
Enter eleCount 16
DSPLIB_DEBUGPRINT  CP 3 status 0
DSPLIB_DEBUGPRINT  DSPLIB_max_d CP 2 status_init 0
Enter DSPLIB_max_exec_checkParams
DSPLIB_DEBUGPRINT  DSPLIB_max_d CP 3 status_opt 0
DSPLIB_DEBUGPRINT Enter DSPLIB_max_exec
DSPLIB_DEBUGPRINT pKerPrivArgs->blockSize 512
Enter DSPLIB_max_exec_ci
Enter eleCount 16
DSPLIB_DEBUGPRINT blockSize 512
DSPLIB_DEBUGPRINT Enter DSPLIB_max_exec
DSPLIB_DEBUGPRINT pKerPrivArgs->blockSize 512
Enter DSPLIB_max_exec_ci
Enter eleCount 16
DSPLIB_DEBUGPRINT blockSize 512
DSPLIB_DEBUGPRINT Enter DSPLIB_max_exec
DSPLIB_DEBUGPRINT pKerPrivArgs->blockSize 512
Enter DSPLIB_max_exec_ci
Enter eleCount 16
DSPLIB_DEBUGPRINT blockSize 512
DSPLIB_DEBUGPRINT Enter DSPLIB_max_exec
DSPLIB_DEBUGPRINT pKerPrivArgs->blockSize 512
Enter DSPLIB_max_exec_ci
Enter eleCount 16
DSPLIB_DEBUGPRINT blockSize 512
DSPLIB_DEBUGPRINT Enter DSPLIB_max_exec
DSPLIB_DEBUGPRINT pKerPrivArgs->blockSize 512
Enter DSPLIB_max_exec_ci
Enter eleCount 16
DSPLIB_DEBUGPRINT blockSize 512
DSPLIB_DEBUGPRINT Enter DSPLIB_max_exec
DSPLIB_DEBUGPRINT pKerPrivArgs->blockSize 512
Enter DSPLIB_max_exec_ci
Enter eleCount 16
DSPLIB_DEBUGPRINT blockSize 512
Enter DSPLIB_max_init_checkParams
DSPLIB_DEBUGPRINT  DSPLIB_max_d CP 4 status_opt 0
DSPLIB_DEBUGPRINT Enter DSPLIB_max_init
DSPLIB_DEBUGPRINT DSPLIB_max_init pKerPrivArgs->blockSize 512 bufParamsIn->data_type 12
DSPLIB_DEBUGPRINT  CP 3 status 0
DSPLIB_DEBUGPRINT  DSPLIB_max_d CP 5
DSPLIB_DEBUGPRINT Enter DSPLIB_max_exec
DSPLIB_DEBUGPRINT pKerPrivArgs->blockSize 512
Enter DSPLIB_max_exec_cn
Enter pInLocal 64800380  pOut 80200000
counter 0 a 0 b -2147483648
counter 0 y 0
counter 1 a 0 b 0
counter 1 y 0
counter 2 a 0 b -2147483648
counter 2 y 0
counter 3 a 0 b 0
counter 3 y 0
counter 4 a 0 b -1073741824
counter 4 y 0
counter 5 a 0 b -2147483648
counter 5 y 0
counter 6 a 0 b 0
counter 6 y 0
counter 7 a 0 b 0
counter 7 y 0
counter 8 a 0 b 0
counter 8 y 0
DSPLIB_DEBUGPRINT  DSPLIB_max_d CP 6 status_nat 0
DSPLIB_DEBUGPRINT  DSPLIB_max_d CP 7 comparisonDone 1 status_nat_vs_opt 1
DSPLIB_DEBUGPRINT  DSPLIB_max_d CP 8 status_nat_vs_opt 1 status_ref_vs_opt 1 currentTestFail 0
DSPLIB_DEBUGPRINT  DSPLIB_max_d CP 8 status_init 0 status_opt 0 status_nat 0
DSPLIB_DEBUGPRINT  DSPLIB_max_d CP 8 fail 0
|   1 |   2 | PASS   |     512 |    2962225229 |      2284796623 |    7051787175 |             0 |           0 |             0 |           0 | RANDOM generated input | Data size = 512 Data Type 12
Test Pass!
Test    0: Cold Cycles = -2010170673, Warm Cycles = 1687469968, Warm Cycles WRB = 1085531726
Enter DSPLIB_max_init_checkParams
Enter DSPLIB_max_init_checkParams
|   2 |1000 | PASS   |       0 |             0 |               0 |             0 |             0 |         nan |             0 |         nan | COVERAGE TEST
Enter DSPLIB_max_init_checkParams
Enter DSPLIB_max_init_checkParams
|   3 |1001 | PASS   |       0 |             0 |               0 |             0 |             0 |         nan |             0 |         nan | COVERAGE TEST
Enter DSPLIB_max_init_checkParams
Enter DSPLIB_max_init_checkParams
|   4 |1002 | PASS   |       0 |             0 |               0 |             0 |             0 |         nan |             0 |         nan | COVERAGE TEST
Enter DSPLIB_max_exec_checkParams
|   5 |1003 | PASS   |       0 |             0 |               0 |             0 |             0 |         nan |             0 |         nan | COVERAGE TEST
Enter DSPLIB_max_exec_checkParams
|   6 |1004 | PASS   |       0 |             0 |               0 |             0 |             0 |         nan |             0 |         nan | COVERAGE TEST
DSPLIB_DEBUGPRINT Enter DSPLIB_max_init
DSPLIB_DEBUGPRINT DSPLIB_max_init pKerPrivArgs->blockSize -1402269312 bufParamsIn->data_type 3
DSPLIB_DEBUGPRINT  CP 2 status 3
DSPLIB_DEBUGPRINT  CP 3 status 3
DSPLIB_DEBUGPRINT Enter DSPLIB_max_init
DSPLIB_DEBUGPRINT DSPLIB_max_init pKerPrivArgs->blockSize -1402269312 bufParamsIn->data_type 3
DSPLIB_DEBUGPRINT  CP 3 status 3
|   7 |1005 | PASS   |       0 |             0 |               0 |             0 |             0 |         nan |             0 |         nan | COVERAGE TEST
Enter DSPLIB_max_init_checkParams
Enter DSPLIB_max_init_checkParams
|   8 |1006 | PASS   |       0 |             0 |               0 |             0 |             0 |         nan |             0 |         nan | COVERAGE TEST
DSPLIB_DEBUGPRINT Enter DSPLIB_max_init
DSPLIB_DEBUGPRINT DSPLIB_max_init pKerPrivArgs->blockSize 8 bufParamsIn->data_type 13
DSPLIB_DEBUGPRINT  CP 3 status 0
DSPLIB_DEBUGPRINT Enter DSPLIB_max_init
DSPLIB_DEBUGPRINT DSPLIB_max_init pKerPrivArgs->blockSize 8 bufParamsIn->data_type 13
Enter eleCount 8
DSPLIB_DEBUGPRINT  CP 3 status 0
|   9 |1007 | PASS   |       0 |             0 |               0 |             0 |             0 |         nan |             0 |         nan | COVERAGE TEST
DSPLIB_DEBUGPRINT Enter DSPLIB_max_init
DSPLIB_DEBUGPRINT DSPLIB_max_init pKerPrivArgs->blockSize 4 bufParamsIn->data_type 13
DSPLIB_DEBUGPRINT  CP 3 status 0
DSPLIB_DEBUGPRINT Enter DSPLIB_max_init
DSPLIB_DEBUGPRINT DSPLIB_max_init pKerPrivArgs->blockSize 4 bufParamsIn->data_type 13
Enter eleCount 8
DSPLIB_DEBUGPRINT  CP 3 status 0
|  10 |1008 | PASS   |       0 |             0 |               0 |             0 |             0 |         nan |             0 |         nan | COVERAGE TEST
DSPLIB_DEBUGPRINT Enter DSPLIB_max_init
DSPLIB_DEBUGPRINT DSPLIB_max_init pKerPrivArgs->blockSize 14 bufParamsIn->data_type 13
DSPLIB_DEBUGPRINT  CP 3 status 0
DSPLIB_DEBUGPRINT Enter DSPLIB_max_init
DSPLIB_DEBUGPRINT DSPLIB_max_init pKerPrivArgs->blockSize 14 bufParamsIn->data_type 13
Enter eleCount 8
DSPLIB_DEBUGPRINT  CP 3 status 0
|  11 |1009 | PASS   |       0 |             0 |               0 |             0 |             0 |         nan |             0 |         nan | COVERAGE TEST
Test Pass!

    Regards,
    Shabary S Sundar

  • 0 in reply to Srinivas Thalam
    TI__Intellectual 1920 points

    Hi,
    Please use the linker script located at: "ti-processor-sdk-rtos-j721e-evm-11_00_00_06\dsplib\cmake\linkers\C7100\lnk.cmd" and make sure that you are using SOC as C7100.

    Regards,
    Shabary S Sundar

  • 0 in reply to Shabary S Sundar
    Prodigy 90 points

    Hi Shabary, 

    We are trying to run the .out you shared via mail. 
    Can you please confirm the steps we followed are correct which we have shared in the pdf through mail ?

    Regards,
    Srinivas Thalam

  • 0 in reply to Shabary S Sundar
    Prodigy 90 points

    Hi Shabary,

    I have tried running the .out which you have shared, below error popped out.
    Do we need source code while loading the .out on c7x core.

    No source available for "main() at /home/thalamr/workspace_v_latest/rgbir_instrinsic/Debug/test_DSPLIB_max_C7100.out:{3} 0x70411980{4}" 

    Regards,
    Srinivas Thalam

  • 0 in reply to Srinivas Thalam
    TI__Intellectual 1920 points

    Hi,

    Shabary S Sundar said:
    Please use the linker script located at: "ti-processor-sdk-rtos-j721e-evm-11_00_00_06\dsplib\cmake\linkers\C7100\lnk.cmd" and make sure that you are using SOC as C7100

    Have you tried this?

    Regards,
    Shabary S Sundar

  • 0 in reply to Shabary S Sundar
    Prodigy 90 points

    Hi Shabary,

    We could see a some improvement. Finally .out is loaded on the core after using the "ti-processor-sdk-rtos-j721e-evm-11_00_00_06\dsplib\cmake\linkers\C7100\lnk.cmd" file.

    Please give us a moment, we will confirm everything is fine.

    Thanking you in Advance.


    Regards,
    Srinivas Thalam

  • 0 in reply to Srinivas Thalam
    TI__Expert 4280 points

    Hi Srinivas,

    Srinivas Thalam said:
    Can you please confirm the steps we followed are correct which we have shared in the pdf through mail ?

    Yes, your steps are correct. 

    Please ensure the following:

    1. Use the lnk.cmd file located at: "ti-processor-sdk-rtos-j721e-evm-11_00_00_06\dsplib\cmake\linkers\C7100\lnk.cmd"

    2. Confirm that you are building for C7100.

    Regards,

    Betsy Varughese

  • 0 in reply to Srinivas Thalam
    TI__Expert 4280 points

    Hi Srinivas,

    Srinivas Thalam said:
    Please give us a moment, we will confirm everything is fine.

    Kindly confirm from your side. In the meantime, I’ll move this to the waiting stage.

    Regards,

    Betsy Varughese

  • 0 in reply to Betsy Varughese
    Prodigy 90 points

    Hi Betsy,
    Hi Shabary,

    After using the "ti-processor-sdk-rtos-j721e-evm-11_00_00_06\dsplib\cmake\linkers\C7100\lnk.cmd" file for linking, our issue is solved.

    Thank you very much for your on-time support.

    Thanks & Regards,
    Srinivas Thalam