TDA4VM: CCS 12.8 issue in flashing and debugging

Hi Tomislav,

Are you able to see the "Happy Debugging!!" log from running the launch.js script?

Since you are using SDK 7.2, I would recommend testing with an older version of CCS. Based on the documentation, SDK 7.2 was tested and validated on CCS version 9.3. It has not been tested or validated for CCS 12.8 as this is a new version for the newest SDKs. Could you test with CCS version 9.3?

Thanks,

Neehar

Hello Neehar,

I have installed CCS9.3 and didn't make a change. But what did make a change is setting loadSciserverFlag to 0 in launch.js file. I believe the problem was SciServer was loaded there and then since I want my AUTOSAR application to run on it it failed during overwrite.

Now I am able to reach main( in debugger but when target is run eventually it jumps to 0x4 address and from there to 0x0. Do you know what could be the issue?

IMO it could be due to some wrong placement of rst and interrupt vector tables. I have used RESETVECTOR placement refference from Jacinto PSDK 7.2. and here is the .ld file used. Could you crosscheck if all the dependencies are correctly placed for MCU_R5_0 core?

/**********************************************************************************************************************
 *  EXAMPLE CODE ONLY
 *  -------------------------------------------------------------------------------------------------------------------
 *  This Example Code is only intended for illustrating an example of a possible BSW integration and BSW configuration.
 *  The Example Code has not passed any quality control measures and may be incomplete. The Example Code is neither
 *  intended nor qualified for use in series production. The Example Code as well as any of its modifications and/or
 *  implementations must be tested with diligent care and must comply with all quality requirements which are necessary
 *  according to the state of the art before their use.
 *********************************************************************************************************************/

/* Stack Sizes for various modes */
__IRQ_STACK_SIZE = 0x1000;
__FIQ_STACK_SIZE = 0x1000;
__ABORT_STACK_SIZE = 0x1000;
__UND_STACK_SIZE = 0x1000;
__SVC_STACK_SIZE = 0x1000;
__STACK_SIZE = 0x20000;

MEMORY
{
  OCMCRAM_Common : ORIGIN = 0x41C3F000 , LENGTH = 0x0000C000 /* 48 KiB */
  OCMCRAM_Common_NonCache : ORIGIN = 0x41C4B000 , LENGTH = 0x00000400 /* 1024 Byte */
  OCMCRAM_Core0 : ORIGIN = 0x41C4B400 , LENGTH = 0x00000400 /* 1024 Byte */
  OCMCRAM_Core1 : ORIGIN = 0x41C4B800 , LENGTH = 0x00000400 /* 1024 Byte */
  OCMCRAM_Core2 : ORIGIN = 0x41C4BC00 , LENGTH = 0x00000400 /* 1024 Byte */
  OCMCRAM_Core3 : ORIGIN = 0x41C4C000 , LENGTH = 0x00000400 /* 1024 Byte */
  OCMCRAM_Core4 : ORIGIN = 0x41C4C400 , LENGTH = 0x00000400 /* 1024 Byte */
  OCMCRAM_Core5 : ORIGIN = 0x41C4C800 , LENGTH = 0x00000400 /* 1024 Byte */
  DDR0 : ORIGIN = 0x97000000 , LENGTH = 0x01000000 /* 16 MiB */

  VECTORS (X)             : origin=0x41CE2000 length=0x1000
  RESET_VECTORS (X)       : origin=0x41CE3000 length=0x100
  /* j721e MCMS3 locations */
  /* j721e Reserved Memory for ARM Trusted Firmware */
  MSMC3_ARM_FW   (RWIX)   : origin=0x70000000 length=0x40000         /* 256KB */
  MSMC3   (RWIX)          : origin=0x70040000 length=0x7B0000        /* 8MB - 320KB */
  /* j721e Reserved Memory for DMSC Firmware */
  MSMC3_DMSC_FW  (RWIX)   : origin=0x707F0000 length=0x10000         /* 64KB */
}

SECTIONS
{
  .intvecs 	     : {} palign(8) 	 > VECTORS
  .intc_text 	 : {} palign(8)  	 > VECTORS
  .rstvectors    : {} palign(8)      > RESET_VECTORS
  .bootCode      : {} palign(8)      > MSMC3
  .sysmem        : {}                > MSMC3
  .startupData   : {} palign(8)      > MSMC3, type = NOINIT
  .boardcfg_data : {} palign(128)    > MSMC3

  .stack      : {} align(4)       > DDR0  (HIGH)
  .irqStack   : {. = . + __IRQ_STACK_SIZE;} align(4)      > DDR0  (HIGH)
  RUN_START(__IRQ_STACK_START)
  RUN_END(__IRQ_STACK_END)
  .fiqStack   : {. = . + __FIQ_STACK_SIZE;} align(4)      > DDR0  (HIGH)
  RUN_START(__FIQ_STACK_START)
  RUN_END(__FIQ_STACK_END)
  .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)    > DDR0  (HIGH)
  RUN_START(__ABORT_STACK_START)
  RUN_END(__ABORT_STACK_END)
  .undStack   : {. = . + __UND_STACK_SIZE;} align(4)      > DDR0  (HIGH)
  RUN_START(__UND_STACK_START)
  RUN_END(__UND_STACK_END)
  .svcStack   : {. = . + __SVC_STACK_SIZE;} align(4)      > DDR0  (HIGH)
  RUN_START(__SVC_STACK_START)
  RUN_END(__SVC_STACK_END)

  .OS_DATA_CORE0_VAR_INIT : ALIGN(4)
  {
    _OS_DATA_CORE0_VAR_INIT_START = .;
    *(.OS_CORE0_VAR)
    *(.OS_SystemApplication_OsCore0_VAR)
    . = ALIGN(4);
    _OS_DATA_CORE0_VAR_INIT_END = . - 1;
    _OS_DATA_CORE0_VAR_INIT_LIMIT = .;
  } > DDR0, RUN > DDR0,
  LOAD_START(_OS_DATA_CORE0_VAR_INIT_ROM_START),
  LOAD_END(_OS_DATA_CORE0_VAR_INIT_ROM_LIMIT)

  .OS_DATA_CORE0_VAR_NOINIT :
  {
    _OS_DATA_CORE0_VAR_NOINIT_START = .;
    *(.OS_CORE0_VAR_NOINIT)
    *(.OS_SystemApplication_OsCore0_VAR_NOINIT)
    _OS_DATA_CORE0_VAR_NOINIT_END = . - 1;
    _OS_DATA_CORE0_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_DATA_CORE0_VAR_ZERO_INIT : ALIGN(4)
  {
    _OS_DATA_CORE0_VAR_ZERO_INIT_START = .;
    *(.OS_SystemApplication_OsCore0_VAR_ZERO_INIT)
    . = ALIGN(4);
    _OS_DATA_CORE0_VAR_ZERO_INIT_END = . - 1;
    _OS_DATA_CORE0_VAR_ZERO_INIT_LIMIT = .;
  } > DDR0

  .OS_DATA_CORE0_VAR_LABELS :
  {
    _OS_DATA_CORE0_VAR_ALL_START = _OS_DATA_CORE0_VAR_INIT_START;
    _OS_DATA_CORE0_VAR_ALL_END = _OS_DATA_CORE0_VAR_ZERO_INIT_END;
    _OS_DATA_CORE0_VAR_ALL_LIMIT = _OS_DATA_CORE0_VAR_ZERO_INIT_LIMIT;
  }

  .OS_DATA_CORE0_VAR_INIT_NoCache : ALIGN(4)
  {
    _OS_DATA_CORE0_VAR_INIT_NoCache_START = .;
    *(.OS_CORE0_VAR_NOCACHE)
    *(.OS_SystemApplication_OsCore0_VAR_NOCACHE)
    . = ALIGN(4);
    _OS_DATA_CORE0_VAR_INIT_NoCache_END = . - 1;
    _OS_DATA_CORE0_VAR_INIT_NoCache_LIMIT = .;
  } > DDR0, RUN > OCMCRAM_Common_NonCache,
  LOAD_START(_OS_DATA_CORE0_VAR_INIT_NoCache_ROM_START),
  LOAD_END(_OS_DATA_CORE0_VAR_INIT_NoCache_ROM_LIMIT)

  .OS_DATA_CORE0_VAR_NOINIT_NoCache :
  {
    _OS_DATA_CORE0_VAR_NOINIT_NoCache_START = .;
    *(.OS_CORE0_VAR_NOCACHE_NOINIT)
    *(.OS_SystemApplication_OsCore0_VAR_NOCACHE_NOINIT)
    _OS_DATA_CORE0_VAR_NOINIT_NoCache_END = . - 1;
    _OS_DATA_CORE0_VAR_NOINIT_NoCache_LIMIT = .;
  } > OCMCRAM_Common_NonCache

  .OS_DATA_CORE0_VAR_ZERO_INIT_NoCache : ALIGN(4)
  {
    _OS_DATA_CORE0_VAR_ZERO_INIT_NoCache_START = .;
    *(.OS_SystemApplication_OsCore0_VAR_NOCACHE_ZERO_INIT)
    . = ALIGN(4);
    _OS_DATA_CORE0_VAR_ZERO_INIT_NoCache_END = . - 1;
    _OS_DATA_CORE0_VAR_ZERO_INIT_NoCache_LIMIT = .;
  } > OCMCRAM_Common_NonCache

  .OS_DATA_CORE0_VAR_NoCache_LABELS :
  {
    _OS_DATA_CORE0_VAR_NoCache_ALL_START = _OS_DATA_CORE0_VAR_INIT_NoCache_START;
    _OS_DATA_CORE0_VAR_NoCache_ALL_END = _OS_DATA_CORE0_VAR_ZERO_INIT_NoCache_END;
    _OS_DATA_CORE0_VAR_NoCache_ALL_LIMIT = _OS_DATA_CORE0_VAR_ZERO_INIT_NoCache_LIMIT;
  }

  .OS_DATA_CORE1_VAR_INIT : ALIGN(4)
  {
    _OS_DATA_CORE1_VAR_INIT_START = .;
    . = ALIGN(4);
    _OS_DATA_CORE1_VAR_INIT_END = . - 1;
    _OS_DATA_CORE1_VAR_INIT_LIMIT = .;
  } > DDR0, RUN > DDR0,
  LOAD_START(_OS_DATA_CORE1_VAR_INIT_ROM_START),
  LOAD_END(_OS_DATA_CORE1_VAR_INIT_ROM_LIMIT)

  .OS_DATA_CORE1_VAR_NOINIT :
  {
    _OS_DATA_CORE1_VAR_NOINIT_START = .;
    _OS_DATA_CORE1_VAR_NOINIT_END = . - 1;
    _OS_DATA_CORE1_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_DATA_CORE1_VAR_ZERO_INIT : ALIGN(4)
  {
    _OS_DATA_CORE1_VAR_ZERO_INIT_START = .;
    . = ALIGN(4);
    _OS_DATA_CORE1_VAR_ZERO_INIT_END = . - 1;
    _OS_DATA_CORE1_VAR_ZERO_INIT_LIMIT = .;
  } > DDR0

  .OS_DATA_CORE1_VAR_LABELS :
  {
    _OS_DATA_CORE1_VAR_ALL_START = _OS_DATA_CORE1_VAR_INIT_START;
    _OS_DATA_CORE1_VAR_ALL_END = _OS_DATA_CORE1_VAR_ZERO_INIT_END;
    _OS_DATA_CORE1_VAR_ALL_LIMIT = _OS_DATA_CORE1_VAR_ZERO_INIT_LIMIT;
  }

  .OS_DATA_CORE1_VAR_INIT_NoCache : ALIGN(4)
  {
    _OS_DATA_CORE1_VAR_INIT_NoCache_START = .;
    . = ALIGN(4);
    _OS_DATA_CORE1_VAR_INIT_NoCache_END = . - 1;
    _OS_DATA_CORE1_VAR_INIT_NoCache_LIMIT = .;
  } > DDR0, RUN > OCMCRAM_Common_NonCache,
  LOAD_START(_OS_DATA_CORE1_VAR_INIT_NoCache_ROM_START),
  LOAD_END(_OS_DATA_CORE1_VAR_INIT_NoCache_ROM_LIMIT)

  .OS_DATA_CORE1_VAR_NOINIT_NoCache :
  {
    _OS_DATA_CORE1_VAR_NOINIT_NoCache_START = .;
    _OS_DATA_CORE1_VAR_NOINIT_NoCache_END = . - 1;
    _OS_DATA_CORE1_VAR_NOINIT_NoCache_LIMIT = .;
  } > OCMCRAM_Common_NonCache

  .OS_DATA_CORE1_VAR_ZERO_INIT_NoCache : ALIGN(4)
  {
    _OS_DATA_CORE1_VAR_ZERO_INIT_NoCache_START = .;
    . = ALIGN(4);
    _OS_DATA_CORE1_VAR_ZERO_INIT_NoCache_END = . - 1;
    _OS_DATA_CORE1_VAR_ZERO_INIT_NoCache_LIMIT = .;
  } > OCMCRAM_Common_NonCache

  .OS_DATA_CORE1_VAR_NoCache_LABELS :
  {
    _OS_DATA_CORE1_VAR_NoCache_ALL_START = _OS_DATA_CORE1_VAR_INIT_NoCache_START;
    _OS_DATA_CORE1_VAR_NoCache_ALL_END = _OS_DATA_CORE1_VAR_ZERO_INIT_NoCache_END;
    _OS_DATA_CORE1_VAR_NoCache_ALL_LIMIT = _OS_DATA_CORE1_VAR_ZERO_INIT_NoCache_LIMIT;
  }

  .OS_DATA_CORE2_VAR_INIT : ALIGN(4)
  {
    _OS_DATA_CORE2_VAR_INIT_START = .;
    . = ALIGN(4);
    _OS_DATA_CORE2_VAR_INIT_END = . - 1;
    _OS_DATA_CORE2_VAR_INIT_LIMIT = .;
  } > DDR0, RUN > DDR0,
  LOAD_START(_OS_DATA_CORE2_VAR_INIT_ROM_START),
  LOAD_END(_OS_DATA_CORE2_VAR_INIT_ROM_LIMIT)

  .OS_DATA_CORE2_VAR_NOINIT :
  {
    _OS_DATA_CORE2_VAR_NOINIT_START = .;
    _OS_DATA_CORE2_VAR_NOINIT_END = . - 1;
    _OS_DATA_CORE2_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_DATA_CORE2_VAR_ZERO_INIT : ALIGN(4)
  {
    _OS_DATA_CORE2_VAR_ZERO_INIT_START = .;
    . = ALIGN(4);
    _OS_DATA_CORE2_VAR_ZERO_INIT_END = . - 1;
    _OS_DATA_CORE2_VAR_ZERO_INIT_LIMIT = .;
  } > DDR0

  .OS_DATA_CORE2_VAR_LABELS :
  {
    _OS_DATA_CORE2_VAR_ALL_START = _OS_DATA_CORE2_VAR_INIT_START;
    _OS_DATA_CORE2_VAR_ALL_END = _OS_DATA_CORE2_VAR_ZERO_INIT_END;
    _OS_DATA_CORE2_VAR_ALL_LIMIT = _OS_DATA_CORE2_VAR_ZERO_INIT_LIMIT;
  }

  .OS_DATA_CORE3_VAR_INIT : ALIGN(4)
  {
    _OS_DATA_CORE3_VAR_INIT_START = .;
    . = ALIGN(4);
    _OS_DATA_CORE3_VAR_INIT_END = . - 1;
    _OS_DATA_CORE3_VAR_INIT_LIMIT = .;
  } > DDR0, RUN > DDR0,
  LOAD_START(_OS_DATA_CORE3_VAR_INIT_ROM_START),
  LOAD_END(_OS_DATA_CORE3_VAR_INIT_ROM_LIMIT)

  .OS_DATA_CORE3_VAR_NOINIT :
  {
    _OS_DATA_CORE3_VAR_NOINIT_START = .;
    _OS_DATA_CORE3_VAR_NOINIT_END = . - 1;
    _OS_DATA_CORE3_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_DATA_CORE3_VAR_ZERO_INIT : ALIGN(4)
  {
    _OS_DATA_CORE3_VAR_ZERO_INIT_START = .;
    . = ALIGN(4);
    _OS_DATA_CORE3_VAR_ZERO_INIT_END = . - 1;
    _OS_DATA_CORE3_VAR_ZERO_INIT_LIMIT = .;
  } > DDR0

  .OS_DATA_CORE3_VAR_LABELS :
  {
    _OS_DATA_CORE3_VAR_ALL_START = _OS_DATA_CORE3_VAR_INIT_START;
    _OS_DATA_CORE3_VAR_ALL_END = _OS_DATA_CORE3_VAR_ZERO_INIT_END;
    _OS_DATA_CORE3_VAR_ALL_LIMIT = _OS_DATA_CORE3_VAR_ZERO_INIT_LIMIT;
  }

  .OS_DATA_CORE4_VAR_INIT : ALIGN(4)
  {
    _OS_DATA_CORE4_VAR_INIT_START = .;
    . = ALIGN(4);
    _OS_DATA_CORE4_VAR_INIT_END = . - 1;
    _OS_DATA_CORE4_VAR_INIT_LIMIT = .;
  } > DDR0, RUN > DDR0,
  LOAD_START(_OS_DATA_CORE4_VAR_INIT_ROM_START),
  LOAD_END(_OS_DATA_CORE4_VAR_INIT_ROM_LIMIT)

  .OS_DATA_CORE4_VAR_NOINIT :
  {
    _OS_DATA_CORE4_VAR_NOINIT_START = .;
    _OS_DATA_CORE4_VAR_NOINIT_END = . - 1;
    _OS_DATA_CORE4_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_DATA_CORE4_VAR_ZERO_INIT : ALIGN(4)
  {
    _OS_DATA_CORE4_VAR_ZERO_INIT_START = .;
    . = ALIGN(4);
    _OS_DATA_CORE4_VAR_ZERO_INIT_END = . - 1;
    _OS_DATA_CORE4_VAR_ZERO_INIT_LIMIT = .;
  } > DDR0

  .OS_DATA_CORE4_VAR_LABELS :
  {
    _OS_DATA_CORE4_VAR_ALL_START = _OS_DATA_CORE4_VAR_INIT_START;
    _OS_DATA_CORE4_VAR_ALL_END = _OS_DATA_CORE4_VAR_ZERO_INIT_END;
    _OS_DATA_CORE4_VAR_ALL_LIMIT = _OS_DATA_CORE4_VAR_ZERO_INIT_LIMIT;
  }

  .OS_DATA_CORE5_VAR_INIT : ALIGN(4)
  {
    _OS_DATA_CORE5_VAR_INIT_START = .;
    . = ALIGN(4);
    _OS_DATA_CORE5_VAR_INIT_END = . - 1;
    _OS_DATA_CORE5_VAR_INIT_LIMIT = .;
  } > DDR0, RUN > DDR0,
  LOAD_START(_OS_DATA_CORE5_VAR_INIT_ROM_START),
  LOAD_END(_OS_DATA_CORE5_VAR_INIT_ROM_LIMIT)

  .OS_DATA_CORE5_VAR_NOINIT :
  {
    _OS_DATA_CORE5_VAR_NOINIT_START = .;
    _OS_DATA_CORE5_VAR_NOINIT_END = . - 1;
    _OS_DATA_CORE5_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_DATA_CORE5_VAR_ZERO_INIT : ALIGN(4)
  {
    _OS_DATA_CORE5_VAR_ZERO_INIT_START = .;
    . = ALIGN(4);
    _OS_DATA_CORE5_VAR_ZERO_INIT_END = . - 1;
    _OS_DATA_CORE5_VAR_ZERO_INIT_LIMIT = .;
  } > DDR0

  .OS_DATA_CORE5_VAR_LABELS :
  {
    _OS_DATA_CORE5_VAR_ALL_START = _OS_DATA_CORE5_VAR_INIT_START;
    _OS_DATA_CORE5_VAR_ALL_END = _OS_DATA_CORE5_VAR_ZERO_INIT_END;
    _OS_DATA_CORE5_VAR_ALL_LIMIT = _OS_DATA_CORE5_VAR_ZERO_INIT_LIMIT;
  }

  .OS_DATA_SHARED_VAR_INIT : ALIGN(4)
  {
    _OS_DATA_SHARED_VAR_INIT_START = .;
    *(.OS_VAR_NOCACHE)
    . = ALIGN(4);
    _OS_DATA_SHARED_VAR_INIT_END = . - 1;
    _OS_DATA_SHARED_VAR_INIT_LIMIT = .;
  } > DDR0, RUN > OCMCRAM_Common_NonCache,
  LOAD_START(_OS_DATA_SHARED_VAR_INIT_ROM_START),
  LOAD_END(_OS_DATA_SHARED_VAR_INIT_ROM_LIMIT)

  .OS_DATA_SHARED_VAR_NOINIT :
  {
    _OS_DATA_SHARED_VAR_NOINIT_START = .;
    *(.OS_BARRIER_CORE0_VAR_NOCACHE_NOINIT)
    *(.OS_CORESTATUS_CORE0_VAR_NOCACHE_NOINIT)
    *(.OS_PUBLIC_CORE0_VAR_NOINIT)
    *(.OS_VAR_NOCACHE_NOINIT)
    _OS_DATA_SHARED_VAR_NOINIT_END = . - 1;
    _OS_DATA_SHARED_VAR_NOINIT_LIMIT = .;
  } > OCMCRAM_Common_NonCache

  .OS_DATA_SHARED_VAR_LABELS :
  {
    _OS_DATA_SHARED_VAR_ALL_START = _OS_DATA_SHARED_VAR_INIT_START;
    _OS_DATA_SHARED_VAR_ALL_END = _OS_DATA_SHARED_VAR_NOINIT_END;
    _OS_DATA_SHARED_VAR_ALL_LIMIT = _OS_DATA_SHARED_VAR_NOINIT_LIMIT;
  }

  .OS_EXCVEC_CORE0_CODE :
  {
    _OS_EXCVEC_CORE0_CODE_START = .;
    *(.OS_EXCVEC_CORE0_CODE)
    _OS_EXCVEC_CORE0_CODE_END = . - 1;
    _OS_EXCVEC_CORE0_CODE_LIMIT = .;
  } > OCMCRAM_Core0

  .OS_EXCVEC_CORE0_CODE_LABELS :
  {
    _OS_EXCVEC_CORE0_CODE_ALL_START = _OS_EXCVEC_CORE0_CODE_START;
    _OS_EXCVEC_CORE0_CODE_ALL_END = _OS_EXCVEC_CORE0_CODE_END;
    _OS_EXCVEC_CORE0_CODE_ALL_LIMIT = _OS_EXCVEC_CORE0_CODE_LIMIT;
  }

  .OS_EXCVEC_CORE0_CONST :
  {
    _OS_EXCVEC_CORE0_CONST_START = .;
    *(.OS_EXCVEC_CORE0_CONST)
    _OS_EXCVEC_CORE0_CONST_END = . - 1;
    _OS_EXCVEC_CORE0_CONST_LIMIT = .;
  } > OCMCRAM_Common

  .OS_EXCVEC_CORE0_CONST_LABELS :
  {
    _OS_EXCVEC_CORE0_CONST_ALL_START = _OS_EXCVEC_CORE0_CONST_START;
    _OS_EXCVEC_CORE0_CONST_ALL_END = _OS_EXCVEC_CORE0_CONST_END;
    _OS_EXCVEC_CORE0_CONST_ALL_LIMIT = _OS_EXCVEC_CORE0_CONST_LIMIT;
  }

  .OS_EXCVEC_CORE1_CODE :
  {
    _OS_EXCVEC_CORE1_CODE_START = .;
    _OS_EXCVEC_CORE1_CODE_END = . - 1;
    _OS_EXCVEC_CORE1_CODE_LIMIT = .;
  } > OCMCRAM_Core1

  .OS_EXCVEC_CORE1_CODE_LABELS :
  {
    _OS_EXCVEC_CORE1_CODE_ALL_START = _OS_EXCVEC_CORE1_CODE_START;
    _OS_EXCVEC_CORE1_CODE_ALL_END = _OS_EXCVEC_CORE1_CODE_END;
    _OS_EXCVEC_CORE1_CODE_ALL_LIMIT = _OS_EXCVEC_CORE1_CODE_LIMIT;
  }

  .OS_EXCVEC_CORE1_CONST :
  {
    _OS_EXCVEC_CORE1_CONST_START = .;
    _OS_EXCVEC_CORE1_CONST_END = . - 1;
    _OS_EXCVEC_CORE1_CONST_LIMIT = .;
  } > OCMCRAM_Common

  .OS_EXCVEC_CORE1_CONST_LABELS :
  {
    _OS_EXCVEC_CORE1_CONST_ALL_START = _OS_EXCVEC_CORE1_CONST_START;
    _OS_EXCVEC_CORE1_CONST_ALL_END = _OS_EXCVEC_CORE1_CONST_END;
    _OS_EXCVEC_CORE1_CONST_ALL_LIMIT = _OS_EXCVEC_CORE1_CONST_LIMIT;
  }

  .OS_EXCVEC_CORE2_CODE :
  {
    _OS_EXCVEC_CORE2_CODE_START = .;
    _OS_EXCVEC_CORE2_CODE_END = . - 1;
    _OS_EXCVEC_CORE2_CODE_LIMIT = .;
  } > OCMCRAM_Core2

  .OS_EXCVEC_CORE2_CODE_LABELS :
  {
    _OS_EXCVEC_CORE2_CODE_ALL_START = _OS_EXCVEC_CORE2_CODE_START;
    _OS_EXCVEC_CORE2_CODE_ALL_END = _OS_EXCVEC_CORE2_CODE_END;
    _OS_EXCVEC_CORE2_CODE_ALL_LIMIT = _OS_EXCVEC_CORE2_CODE_LIMIT;
  }

  .OS_EXCVEC_CORE2_CONST :
  {
    _OS_EXCVEC_CORE2_CONST_START = .;
    _OS_EXCVEC_CORE2_CONST_END = . - 1;
    _OS_EXCVEC_CORE2_CONST_LIMIT = .;
  } > OCMCRAM_Common

  .OS_EXCVEC_CORE2_CONST_LABELS :
  {
    _OS_EXCVEC_CORE2_CONST_ALL_START = _OS_EXCVEC_CORE2_CONST_START;
    _OS_EXCVEC_CORE2_CONST_ALL_END = _OS_EXCVEC_CORE2_CONST_END;
    _OS_EXCVEC_CORE2_CONST_ALL_LIMIT = _OS_EXCVEC_CORE2_CONST_LIMIT;
  }

  .OS_EXCVEC_CORE3_CODE :
  {
    _OS_EXCVEC_CORE3_CODE_START = .;
    _OS_EXCVEC_CORE3_CODE_END = . - 1;
    _OS_EXCVEC_CORE3_CODE_LIMIT = .;
  } > OCMCRAM_Core3

  .OS_EXCVEC_CORE3_CODE_LABELS :
  {
    _OS_EXCVEC_CORE3_CODE_ALL_START = _OS_EXCVEC_CORE3_CODE_START;
    _OS_EXCVEC_CORE3_CODE_ALL_END = _OS_EXCVEC_CORE3_CODE_END;
    _OS_EXCVEC_CORE3_CODE_ALL_LIMIT = _OS_EXCVEC_CORE3_CODE_LIMIT;
  }

  .OS_EXCVEC_CORE3_CONST :
  {
    _OS_EXCVEC_CORE3_CONST_START = .;
    _OS_EXCVEC_CORE3_CONST_END = . - 1;
    _OS_EXCVEC_CORE3_CONST_LIMIT = .;
  } > OCMCRAM_Common

  .OS_EXCVEC_CORE3_CONST_LABELS :
  {
    _OS_EXCVEC_CORE3_CONST_ALL_START = _OS_EXCVEC_CORE3_CONST_START;
    _OS_EXCVEC_CORE3_CONST_ALL_END = _OS_EXCVEC_CORE3_CONST_END;
    _OS_EXCVEC_CORE3_CONST_ALL_LIMIT = _OS_EXCVEC_CORE3_CONST_LIMIT;
  }

  .OS_EXCVEC_CORE4_CODE :
  {
    _OS_EXCVEC_CORE4_CODE_START = .;
    _OS_EXCVEC_CORE4_CODE_END = . - 1;
    _OS_EXCVEC_CORE4_CODE_LIMIT = .;
  } > OCMCRAM_Core4

  .OS_EXCVEC_CORE4_CODE_LABELS :
  {
    _OS_EXCVEC_CORE4_CODE_ALL_START = _OS_EXCVEC_CORE4_CODE_START;
    _OS_EXCVEC_CORE4_CODE_ALL_END = _OS_EXCVEC_CORE4_CODE_END;
    _OS_EXCVEC_CORE4_CODE_ALL_LIMIT = _OS_EXCVEC_CORE4_CODE_LIMIT;
  }

  .OS_EXCVEC_CORE4_CONST :
  {
    _OS_EXCVEC_CORE4_CONST_START = .;
    _OS_EXCVEC_CORE4_CONST_END = . - 1;
    _OS_EXCVEC_CORE4_CONST_LIMIT = .;
  } > OCMCRAM_Common

  .OS_EXCVEC_CORE4_CONST_LABELS :
  {
    _OS_EXCVEC_CORE4_CONST_ALL_START = _OS_EXCVEC_CORE4_CONST_START;
    _OS_EXCVEC_CORE4_CONST_ALL_END = _OS_EXCVEC_CORE4_CONST_END;
    _OS_EXCVEC_CORE4_CONST_ALL_LIMIT = _OS_EXCVEC_CORE4_CONST_LIMIT;
  }

  .OS_EXCVEC_CORE5_CODE :
  {
    _OS_EXCVEC_CORE5_CODE_START = .;
    _OS_EXCVEC_CORE5_CODE_END = . - 1;
    _OS_EXCVEC_CORE5_CODE_LIMIT = .;
  } > OCMCRAM_Core5

  .OS_EXCVEC_CORE5_CODE_LABELS :
  {
    _OS_EXCVEC_CORE5_CODE_ALL_START = _OS_EXCVEC_CORE5_CODE_START;
    _OS_EXCVEC_CORE5_CODE_ALL_END = _OS_EXCVEC_CORE5_CODE_END;
    _OS_EXCVEC_CORE5_CODE_ALL_LIMIT = _OS_EXCVEC_CORE5_CODE_LIMIT;
  }

  .OS_EXCVEC_CORE5_CONST :
  {
    _OS_EXCVEC_CORE5_CONST_START = .;
    _OS_EXCVEC_CORE5_CONST_END = . - 1;
    _OS_EXCVEC_CORE5_CONST_LIMIT = .;
  } > OCMCRAM_Common

  .OS_EXCVEC_CORE5_CONST_LABELS :
  {
    _OS_EXCVEC_CORE5_CONST_ALL_START = _OS_EXCVEC_CORE5_CONST_START;
    _OS_EXCVEC_CORE5_CONST_ALL_END = _OS_EXCVEC_CORE5_CONST_END;
    _OS_EXCVEC_CORE5_CONST_ALL_LIMIT = _OS_EXCVEC_CORE5_CONST_LIMIT;
  }

  .OS_GLOBALSHARED_CONST :
  {
    _OS_GLOBALSHARED_CONST_START = .;
    *(.OS_GLOBALSHARED_CONST)
    _OS_GLOBALSHARED_CONST_END = . - 1;
    _OS_GLOBALSHARED_CONST_LIMIT = .;
  } > DDR0

  .OS_GLOBALSHARED_CONST_LABELS :
  {
    _OS_GLOBALSHARED_CONST_ALL_START = _OS_GLOBALSHARED_CONST_START;
    _OS_GLOBALSHARED_CONST_ALL_END = _OS_GLOBALSHARED_CONST_END;
    _OS_GLOBALSHARED_CONST_ALL_LIMIT = _OS_GLOBALSHARED_CONST_LIMIT;
  }

  .OS_GLOBALSHARED_VAR_INIT : ALIGN(256)
  {
    _OS_GLOBALSHARED_VAR_INIT_START = .;
    *(.OS_GLOBALSHARED_VAR)
    *(.OS_GLOBALSHARED_VAR_NOCACHE)
    . = ALIGN(256);
    _OS_GLOBALSHARED_VAR_INIT_END = . - 1;
    _OS_GLOBALSHARED_VAR_INIT_LIMIT = .;
  } > DDR0, RUN > OCMCRAM_Common_NonCache,
  LOAD_START(_OS_GLOBALSHARED_VAR_INIT_ROM_START),
  LOAD_END(_OS_GLOBALSHARED_VAR_INIT_ROM_LIMIT)

  .OS_GLOBALSHARED_VAR_NOINIT : ALIGN(256)
  {
    _OS_GLOBALSHARED_VAR_NOINIT_START = .;
    *(.OS_GLOBALSHARED_VAR_NOCACHE_NOINIT)
    *(.OS_GLOBALSHARED_VAR_NOINIT)
    . = ALIGN(256);
    _OS_GLOBALSHARED_VAR_NOINIT_END = . - 1;
    _OS_GLOBALSHARED_VAR_NOINIT_LIMIT = .;
  } > OCMCRAM_Common_NonCache

  .OS_GLOBALSHARED_VAR_ZERO_INIT : ALIGN(256)
  {
    _OS_GLOBALSHARED_VAR_ZERO_INIT_START = .;
    *(.OS_GLOBALSHARED_VAR_NOCACHE_ZERO_INIT)
    *(.OS_GLOBALSHARED_VAR_ZERO_INIT)
    . = ALIGN(256);
    _OS_GLOBALSHARED_VAR_ZERO_INIT_END = . - 1;
    _OS_GLOBALSHARED_VAR_ZERO_INIT_LIMIT = .;
  } > OCMCRAM_Common_NonCache

  .OS_GLOBALSHARED_VAR_LABELS :
  {
    _OS_GLOBALSHARED_VAR_ALL_START = _OS_GLOBALSHARED_VAR_INIT_START;
    _OS_GLOBALSHARED_VAR_ALL_END = _OS_GLOBALSHARED_VAR_ZERO_INIT_END;
    _OS_GLOBALSHARED_VAR_ALL_LIMIT = _OS_GLOBALSHARED_VAR_ZERO_INIT_LIMIT;
  }

  .OS_INTVEC_CODE :
  {
    _OS_INTVEC_CODE_START = .;
    *(.OS_INTVEC_CODE)
    _OS_INTVEC_CODE_END = . - 1;
    _OS_INTVEC_CODE_LIMIT = .;
  } > DDR0

  .OS_INTVEC_CODE_LABELS :
  {
    _OS_INTVEC_CODE_ALL_START = _OS_INTVEC_CODE_START;
    _OS_INTVEC_CODE_ALL_END = _OS_INTVEC_CODE_END;
    _OS_INTVEC_CODE_ALL_LIMIT = _OS_INTVEC_CODE_LIMIT;
  }

  .OS_INTVEC_CONST :
  {
    _OS_INTVEC_CONST_START = .;
    *(.OS_INTVEC_CONST)
    _OS_INTVEC_CONST_END = . - 1;
    _OS_INTVEC_CONST_LIMIT = .;
  } > DDR0

  .OS_INTVEC_CONST_LABELS :
  {
    _OS_INTVEC_CONST_ALL_START = _OS_INTVEC_CONST_START;
    _OS_INTVEC_CONST_ALL_END = _OS_INTVEC_CONST_END;
    _OS_INTVEC_CONST_ALL_LIMIT = _OS_INTVEC_CONST_LIMIT;
  }

  .OS_INTVEC_CORE0_CODE :
  {
    _OS_INTVEC_CORE0_CODE_START = .;
    *(.OS_INTVEC_CORE0_CODE)
    _OS_INTVEC_CORE0_CODE_END = . - 1;
    _OS_INTVEC_CORE0_CODE_LIMIT = .;
  } > DDR0

  .OS_INTVEC_CORE0_CODE_LABELS :
  {
    _OS_INTVEC_CORE0_CODE_ALL_START = _OS_INTVEC_CORE0_CODE_START;
    _OS_INTVEC_CORE0_CODE_ALL_END = _OS_INTVEC_CORE0_CODE_END;
    _OS_INTVEC_CORE0_CODE_ALL_LIMIT = _OS_INTVEC_CORE0_CODE_LIMIT;
  }

  .OS_INTVEC_CORE0_CONST :
  {
    _OS_INTVEC_CORE0_CONST_START = .;
    *(.OS_INTVEC_CORE0_CONST)
    _OS_INTVEC_CORE0_CONST_END = . - 1;
    _OS_INTVEC_CORE0_CONST_LIMIT = .;
  } > DDR0

  .OS_INTVEC_CORE0_CONST_LABELS :
  {
    _OS_INTVEC_CORE0_CONST_ALL_START = _OS_INTVEC_CORE0_CONST_START;
    _OS_INTVEC_CORE0_CONST_ALL_END = _OS_INTVEC_CORE0_CONST_END;
    _OS_INTVEC_CORE0_CONST_ALL_LIMIT = _OS_INTVEC_CORE0_CONST_LIMIT;
  }

  .OS_INTVEC_CORE1_CODE :
  {
    _OS_INTVEC_CORE1_CODE_START = .;
    _OS_INTVEC_CORE1_CODE_END = . - 1;
    _OS_INTVEC_CORE1_CODE_LIMIT = .;
  } > DDR0

  .OS_INTVEC_CORE1_CODE_LABELS :
  {
    _OS_INTVEC_CORE1_CODE_ALL_START = _OS_INTVEC_CORE1_CODE_START;
    _OS_INTVEC_CORE1_CODE_ALL_END = _OS_INTVEC_CORE1_CODE_END;
    _OS_INTVEC_CORE1_CODE_ALL_LIMIT = _OS_INTVEC_CORE1_CODE_LIMIT;
  }

  .OS_INTVEC_CORE1_CONST :
  {
    _OS_INTVEC_CORE1_CONST_START = .;
    _OS_INTVEC_CORE1_CONST_END = . - 1;
    _OS_INTVEC_CORE1_CONST_LIMIT = .;
  } > DDR0

  .OS_INTVEC_CORE1_CONST_LABELS :
  {
    _OS_INTVEC_CORE1_CONST_ALL_START = _OS_INTVEC_CORE1_CONST_START;
    _OS_INTVEC_CORE1_CONST_ALL_END = _OS_INTVEC_CORE1_CONST_END;
    _OS_INTVEC_CORE1_CONST_ALL_LIMIT = _OS_INTVEC_CORE1_CONST_LIMIT;
  }

  .OS_INTVEC_CORE2_CODE :
  {
    _OS_INTVEC_CORE2_CODE_START = .;
    _OS_INTVEC_CORE2_CODE_END = . - 1;
    _OS_INTVEC_CORE2_CODE_LIMIT = .;
  } > DDR0

  .OS_INTVEC_CORE2_CODE_LABELS :
  {
    _OS_INTVEC_CORE2_CODE_ALL_START = _OS_INTVEC_CORE2_CODE_START;
    _OS_INTVEC_CORE2_CODE_ALL_END = _OS_INTVEC_CORE2_CODE_END;
    _OS_INTVEC_CORE2_CODE_ALL_LIMIT = _OS_INTVEC_CORE2_CODE_LIMIT;
  }

  .OS_INTVEC_CORE2_CONST :
  {
    _OS_INTVEC_CORE2_CONST_START = .;
    _OS_INTVEC_CORE2_CONST_END = . - 1;
    _OS_INTVEC_CORE2_CONST_LIMIT = .;
  } > DDR0

  .OS_INTVEC_CORE2_CONST_LABELS :
  {
    _OS_INTVEC_CORE2_CONST_ALL_START = _OS_INTVEC_CORE2_CONST_START;
    _OS_INTVEC_CORE2_CONST_ALL_END = _OS_INTVEC_CORE2_CONST_END;
    _OS_INTVEC_CORE2_CONST_ALL_LIMIT = _OS_INTVEC_CORE2_CONST_LIMIT;
  }

  .OS_INTVEC_CORE3_CODE :
  {
    _OS_INTVEC_CORE3_CODE_START = .;
    _OS_INTVEC_CORE3_CODE_END = . - 1;
    _OS_INTVEC_CORE3_CODE_LIMIT = .;
  } > DDR0

  .OS_INTVEC_CORE3_CODE_LABELS :
  {
    _OS_INTVEC_CORE3_CODE_ALL_START = _OS_INTVEC_CORE3_CODE_START;
    _OS_INTVEC_CORE3_CODE_ALL_END = _OS_INTVEC_CORE3_CODE_END;
    _OS_INTVEC_CORE3_CODE_ALL_LIMIT = _OS_INTVEC_CORE3_CODE_LIMIT;
  }

  .OS_INTVEC_CORE3_CONST :
  {
    _OS_INTVEC_CORE3_CONST_START = .;
    _OS_INTVEC_CORE3_CONST_END = . - 1;
    _OS_INTVEC_CORE3_CONST_LIMIT = .;
  } > DDR0

  .OS_INTVEC_CORE3_CONST_LABELS :
  {
    _OS_INTVEC_CORE3_CONST_ALL_START = _OS_INTVEC_CORE3_CONST_START;
    _OS_INTVEC_CORE3_CONST_ALL_END = _OS_INTVEC_CORE3_CONST_END;
    _OS_INTVEC_CORE3_CONST_ALL_LIMIT = _OS_INTVEC_CORE3_CONST_LIMIT;
  }

  .OS_INTVEC_CORE4_CODE :
  {
    _OS_INTVEC_CORE4_CODE_START = .;
    _OS_INTVEC_CORE4_CODE_END = . - 1;
    _OS_INTVEC_CORE4_CODE_LIMIT = .;
  } > DDR0

  .OS_INTVEC_CORE4_CODE_LABELS :
  {
    _OS_INTVEC_CORE4_CODE_ALL_START = _OS_INTVEC_CORE4_CODE_START;
    _OS_INTVEC_CORE4_CODE_ALL_END = _OS_INTVEC_CORE4_CODE_END;
    _OS_INTVEC_CORE4_CODE_ALL_LIMIT = _OS_INTVEC_CORE4_CODE_LIMIT;
  }

  .OS_INTVEC_CORE4_CONST :
  {
    _OS_INTVEC_CORE4_CONST_START = .;
    _OS_INTVEC_CORE4_CONST_END = . - 1;
    _OS_INTVEC_CORE4_CONST_LIMIT = .;
  } > DDR0

  .OS_INTVEC_CORE4_CONST_LABELS :
  {
    _OS_INTVEC_CORE4_CONST_ALL_START = _OS_INTVEC_CORE4_CONST_START;
    _OS_INTVEC_CORE4_CONST_ALL_END = _OS_INTVEC_CORE4_CONST_END;
    _OS_INTVEC_CORE4_CONST_ALL_LIMIT = _OS_INTVEC_CORE4_CONST_LIMIT;
  }

  .OS_INTVEC_CORE5_CODE :
  {
    _OS_INTVEC_CORE5_CODE_START = .;
    _OS_INTVEC_CORE5_CODE_END = . - 1;
    _OS_INTVEC_CORE5_CODE_LIMIT = .;
  } > DDR0

  .OS_INTVEC_CORE5_CODE_LABELS :
  {
    _OS_INTVEC_CORE5_CODE_ALL_START = _OS_INTVEC_CORE5_CODE_START;
    _OS_INTVEC_CORE5_CODE_ALL_END = _OS_INTVEC_CORE5_CODE_END;
    _OS_INTVEC_CORE5_CODE_ALL_LIMIT = _OS_INTVEC_CORE5_CODE_LIMIT;
  }

  .OS_INTVEC_CORE5_CONST :
  {
    _OS_INTVEC_CORE5_CONST_START = .;
    _OS_INTVEC_CORE5_CONST_END = . - 1;
    _OS_INTVEC_CORE5_CONST_LIMIT = .;
  } > DDR0

  .OS_INTVEC_CORE5_CONST_LABELS :
  {
    _OS_INTVEC_CORE5_CONST_ALL_START = _OS_INTVEC_CORE5_CONST_START;
    _OS_INTVEC_CORE5_CONST_ALL_END = _OS_INTVEC_CORE5_CONST_END;
    _OS_INTVEC_CORE5_CONST_ALL_LIMIT = _OS_INTVEC_CORE5_CONST_LIMIT;
  }

  .OS_OsApplication_Trusted_Core0_VAR_INIT : ALIGN(4)
  {
    _OS_OsApplication_Trusted_Core0_VAR_INIT_START = .;
    *(.OS_OsApplication_Trusted_Core0_VAR)
    *(.OS_OsApplication_Trusted_Core0_VAR_NOCACHE)
    . = ALIGN(4);
    _OS_OsApplication_Trusted_Core0_VAR_INIT_END = . - 1;
    _OS_OsApplication_Trusted_Core0_VAR_INIT_LIMIT = .;
  } > DDR0, RUN > DDR0,
  LOAD_START(_OS_OsApplication_Trusted_Core0_VAR_INIT_ROM_START),
  LOAD_END(_OS_OsApplication_Trusted_Core0_VAR_INIT_ROM_LIMIT)

  .OS_OsApplication_Trusted_Core0_VAR_NOINIT :
  {
    _OS_OsApplication_Trusted_Core0_VAR_NOINIT_START = .;
    *(.OS_OsApplication_Trusted_Core0_VAR_NOCACHE_NOINIT)
    *(.OS_OsApplication_Trusted_Core0_VAR_NOINIT)
    _OS_OsApplication_Trusted_Core0_VAR_NOINIT_END = . - 1;
    _OS_OsApplication_Trusted_Core0_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_OsApplication_Trusted_Core0_VAR_ZERO_INIT : ALIGN(4)
  {
    _OS_OsApplication_Trusted_Core0_VAR_ZERO_INIT_START = .;
    *(.OS_OsApplication_Trusted_Core0_VAR_NOCACHE_ZERO_INIT)
    *(.OS_OsApplication_Trusted_Core0_VAR_ZERO_INIT)
    . = ALIGN(4);
    _OS_OsApplication_Trusted_Core0_VAR_ZERO_INIT_END = . - 1;
    _OS_OsApplication_Trusted_Core0_VAR_ZERO_INIT_LIMIT = .;
  } > DDR0

  .OS_OsApplication_Trusted_Core0_VAR_LABELS :
  {
    _OS_OsApplication_Trusted_Core0_VAR_ALL_START = _OS_OsApplication_Trusted_Core0_VAR_INIT_START;
    _OS_OsApplication_Trusted_Core0_VAR_ALL_END = _OS_OsApplication_Trusted_Core0_VAR_ZERO_INIT_END;
    _OS_OsApplication_Trusted_Core0_VAR_ALL_LIMIT = _OS_OsApplication_Trusted_Core0_VAR_ZERO_INIT_LIMIT;
  }

  .OS_OsApplication_Trusted_Core1_VAR_INIT : ALIGN(4)
  {
    _OS_OsApplication_Trusted_Core1_VAR_INIT_START = .;
    . = ALIGN(4);
    _OS_OsApplication_Trusted_Core1_VAR_INIT_END = . - 1;
    _OS_OsApplication_Trusted_Core1_VAR_INIT_LIMIT = .;
  } > DDR0, RUN > DDR0,
  LOAD_START(_OS_OsApplication_Trusted_Core1_VAR_INIT_ROM_START),
  LOAD_END(_OS_OsApplication_Trusted_Core1_VAR_INIT_ROM_LIMIT)

  .OS_OsApplication_Trusted_Core1_VAR_NOINIT :
  {
    _OS_OsApplication_Trusted_Core1_VAR_NOINIT_START = .;
    _OS_OsApplication_Trusted_Core1_VAR_NOINIT_END = . - 1;
    _OS_OsApplication_Trusted_Core1_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_OsApplication_Trusted_Core1_VAR_ZERO_INIT : ALIGN(4)
  {
    _OS_OsApplication_Trusted_Core1_VAR_ZERO_INIT_START = .;
    . = ALIGN(4);
    _OS_OsApplication_Trusted_Core1_VAR_ZERO_INIT_END = . - 1;
    _OS_OsApplication_Trusted_Core1_VAR_ZERO_INIT_LIMIT = .;
  } > DDR0

  .OS_OsApplication_Trusted_Core1_VAR_LABELS :
  {
    _OS_OsApplication_Trusted_Core1_VAR_ALL_START = _OS_OsApplication_Trusted_Core1_VAR_INIT_START;
    _OS_OsApplication_Trusted_Core1_VAR_ALL_END = _OS_OsApplication_Trusted_Core1_VAR_ZERO_INIT_END;
    _OS_OsApplication_Trusted_Core1_VAR_ALL_LIMIT = _OS_OsApplication_Trusted_Core1_VAR_ZERO_INIT_LIMIT;
  }

  .OS_OsApplication_Trusted_Core2_VAR_INIT : ALIGN(4)
  {
    _OS_OsApplication_Trusted_Core2_VAR_INIT_START = .;
    . = ALIGN(4);
    _OS_OsApplication_Trusted_Core2_VAR_INIT_END = . - 1;
    _OS_OsApplication_Trusted_Core2_VAR_INIT_LIMIT = .;
  } > DDR0, RUN > DDR0,
  LOAD_START(_OS_OsApplication_Trusted_Core2_VAR_INIT_ROM_START),
  LOAD_END(_OS_OsApplication_Trusted_Core2_VAR_INIT_ROM_LIMIT)

  .OS_OsApplication_Trusted_Core2_VAR_NOINIT :
  {
    _OS_OsApplication_Trusted_Core2_VAR_NOINIT_START = .;
    _OS_OsApplication_Trusted_Core2_VAR_NOINIT_END = . - 1;
    _OS_OsApplication_Trusted_Core2_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_OsApplication_Trusted_Core2_VAR_ZERO_INIT : ALIGN(4)
  {
    _OS_OsApplication_Trusted_Core2_VAR_ZERO_INIT_START = .;
    . = ALIGN(4);
    _OS_OsApplication_Trusted_Core2_VAR_ZERO_INIT_END = . - 1;
    _OS_OsApplication_Trusted_Core2_VAR_ZERO_INIT_LIMIT = .;
  } > DDR0

  .OS_OsApplication_Trusted_Core2_VAR_LABELS :
  {
    _OS_OsApplication_Trusted_Core2_VAR_ALL_START = _OS_OsApplication_Trusted_Core2_VAR_INIT_START;
    _OS_OsApplication_Trusted_Core2_VAR_ALL_END = _OS_OsApplication_Trusted_Core2_VAR_ZERO_INIT_END;
    _OS_OsApplication_Trusted_Core2_VAR_ALL_LIMIT = _OS_OsApplication_Trusted_Core2_VAR_ZERO_INIT_LIMIT;
  }

  .OS_OsApplication_Trusted_Core3_VAR_INIT : ALIGN(4)
  {
    _OS_OsApplication_Trusted_Core3_VAR_INIT_START = .;
    . = ALIGN(4);
    _OS_OsApplication_Trusted_Core3_VAR_INIT_END = . - 1;
    _OS_OsApplication_Trusted_Core3_VAR_INIT_LIMIT = .;
  } > DDR0, RUN > DDR0,
  LOAD_START(_OS_OsApplication_Trusted_Core3_VAR_INIT_ROM_START),
  LOAD_END(_OS_OsApplication_Trusted_Core3_VAR_INIT_ROM_LIMIT)

  .OS_OsApplication_Trusted_Core3_VAR_NOINIT :
  {
    _OS_OsApplication_Trusted_Core3_VAR_NOINIT_START = .;
    _OS_OsApplication_Trusted_Core3_VAR_NOINIT_END = . - 1;
    _OS_OsApplication_Trusted_Core3_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_OsApplication_Trusted_Core3_VAR_ZERO_INIT : ALIGN(4)
  {
    _OS_OsApplication_Trusted_Core3_VAR_ZERO_INIT_START = .;
    . = ALIGN(4);
    _OS_OsApplication_Trusted_Core3_VAR_ZERO_INIT_END = . - 1;
    _OS_OsApplication_Trusted_Core3_VAR_ZERO_INIT_LIMIT = .;
  } > DDR0

  .OS_OsApplication_Trusted_Core3_VAR_LABELS :
  {
    _OS_OsApplication_Trusted_Core3_VAR_ALL_START = _OS_OsApplication_Trusted_Core3_VAR_INIT_START;
    _OS_OsApplication_Trusted_Core3_VAR_ALL_END = _OS_OsApplication_Trusted_Core3_VAR_ZERO_INIT_END;
    _OS_OsApplication_Trusted_Core3_VAR_ALL_LIMIT = _OS_OsApplication_Trusted_Core3_VAR_ZERO_INIT_LIMIT;
  }

  .OS_OsApplication_Trusted_Core4_VAR_INIT : ALIGN(4)
  {
    _OS_OsApplication_Trusted_Core4_VAR_INIT_START = .;
    . = ALIGN(4);
    _OS_OsApplication_Trusted_Core4_VAR_INIT_END = . - 1;
    _OS_OsApplication_Trusted_Core4_VAR_INIT_LIMIT = .;
  } > DDR0, RUN > DDR0,
  LOAD_START(_OS_OsApplication_Trusted_Core4_VAR_INIT_ROM_START),
  LOAD_END(_OS_OsApplication_Trusted_Core4_VAR_INIT_ROM_LIMIT)

  .OS_OsApplication_Trusted_Core4_VAR_NOINIT :
  {
    _OS_OsApplication_Trusted_Core4_VAR_NOINIT_START = .;
    _OS_OsApplication_Trusted_Core4_VAR_NOINIT_END = . - 1;
    _OS_OsApplication_Trusted_Core4_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_OsApplication_Trusted_Core4_VAR_ZERO_INIT : ALIGN(4)
  {
    _OS_OsApplication_Trusted_Core4_VAR_ZERO_INIT_START = .;
    . = ALIGN(4);
    _OS_OsApplication_Trusted_Core4_VAR_ZERO_INIT_END = . - 1;
    _OS_OsApplication_Trusted_Core4_VAR_ZERO_INIT_LIMIT = .;
  } > DDR0

  .OS_OsApplication_Trusted_Core4_VAR_LABELS :
  {
    _OS_OsApplication_Trusted_Core4_VAR_ALL_START = _OS_OsApplication_Trusted_Core4_VAR_INIT_START;
    _OS_OsApplication_Trusted_Core4_VAR_ALL_END = _OS_OsApplication_Trusted_Core4_VAR_ZERO_INIT_END;
    _OS_OsApplication_Trusted_Core4_VAR_ALL_LIMIT = _OS_OsApplication_Trusted_Core4_VAR_ZERO_INIT_LIMIT;
  }

  .OS_OsApplication_Trusted_Core5_VAR_INIT : ALIGN(4)
  {
    _OS_OsApplication_Trusted_Core5_VAR_INIT_START = .;
    . = ALIGN(4);
    _OS_OsApplication_Trusted_Core5_VAR_INIT_END = . - 1;
    _OS_OsApplication_Trusted_Core5_VAR_INIT_LIMIT = .;
  } > DDR0, RUN > DDR0,
  LOAD_START(_OS_OsApplication_Trusted_Core5_VAR_INIT_ROM_START),
  LOAD_END(_OS_OsApplication_Trusted_Core5_VAR_INIT_ROM_LIMIT)

  .OS_OsApplication_Trusted_Core5_VAR_NOINIT :
  {
    _OS_OsApplication_Trusted_Core5_VAR_NOINIT_START = .;
    _OS_OsApplication_Trusted_Core5_VAR_NOINIT_END = . - 1;
    _OS_OsApplication_Trusted_Core5_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_OsApplication_Trusted_Core5_VAR_ZERO_INIT : ALIGN(4)
  {
    _OS_OsApplication_Trusted_Core5_VAR_ZERO_INIT_START = .;
    . = ALIGN(4);
    _OS_OsApplication_Trusted_Core5_VAR_ZERO_INIT_END = . - 1;
    _OS_OsApplication_Trusted_Core5_VAR_ZERO_INIT_LIMIT = .;
  } > DDR0

  .OS_OsApplication_Trusted_Core5_VAR_LABELS :
  {
    _OS_OsApplication_Trusted_Core5_VAR_ALL_START = _OS_OsApplication_Trusted_Core5_VAR_INIT_START;
    _OS_OsApplication_Trusted_Core5_VAR_ALL_END = _OS_OsApplication_Trusted_Core5_VAR_ZERO_INIT_END;
    _OS_OsApplication_Trusted_Core5_VAR_ALL_LIMIT = _OS_OsApplication_Trusted_Core5_VAR_ZERO_INIT_LIMIT;
  }

  .OS_STACKS_CORE0_VAR_NOINIT :
  {
    _OS_STACKS_CORE0_VAR_NOINIT_START = .;
    . = ALIGN(1024);
    *(.OS_STACK_DEFAULT_BSW_ASYNC_TASK_CORE0_VAR_NOINIT)
    . = ALIGN(1024);
    *(.OS_STACK_OSCORE0_ERROR_VAR_NOINIT)
    . = ALIGN(1024);
    *(.OS_STACK_OSCORE0_INIT_VAR_NOINIT)
    . = ALIGN(1024);
    *(.OS_STACK_OSCORE0_ISR_CORE_VAR_NOINIT)
    . = ALIGN(1024);
    *(.OS_STACK_OSCORE0_KERNEL_VAR_NOINIT)
    . = ALIGN(1024);
    *(.OS_STACK_OSCORE0_TASK_PRIO10_VAR_NOINIT)
    . = ALIGN(1024);
    *(.OS_STACK_OSCORE0_TASK_PRIO40_VAR_NOINIT)
    . = ALIGN(1024);
    *(.OS_STACK_OSCORE0_TASK_PRIO4294967295_VAR_NOINIT)
    . = ALIGN(1024);
    *(.OS_STACK_OSCORE0_TASK_PRIO45_VAR_NOINIT)
    . = ALIGN(1024);
    *(.OS_STACK_OSCORE0_TASK_PRIO49_VAR_NOINIT)
    . = ALIGN(1024);
    *(.OS_STACK_OSCORE0_TASK_PRIO50_VAR_NOINIT)
    . = ALIGN(1024);
    *(.OS_STACK_STARTAPPLICATION_APPL_TASK_CORE0_VAR_NOINIT)
    . = ALIGN(16384);
    _OS_STACKS_CORE0_VAR_NOINIT_END = . - 1;
    _OS_STACKS_CORE0_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_STACKS_CORE0_VAR_LABELS :
  {
    _OS_STACKS_CORE0_VAR_ALL_START = _OS_STACKS_CORE0_VAR_NOINIT_START;
    _OS_STACKS_CORE0_VAR_ALL_END = _OS_STACKS_CORE0_VAR_NOINIT_END;
    _OS_STACKS_CORE0_VAR_ALL_LIMIT = _OS_STACKS_CORE0_VAR_NOINIT_LIMIT;
  }

  .OS_STACKS_CORE1_VAR_NOINIT :
  {
    _OS_STACKS_CORE1_VAR_NOINIT_START = .;
    . = ALIGN(16384);
    _OS_STACKS_CORE1_VAR_NOINIT_END = . - 1;
    _OS_STACKS_CORE1_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_STACKS_CORE1_VAR_LABELS :
  {
    _OS_STACKS_CORE1_VAR_ALL_START = _OS_STACKS_CORE1_VAR_NOINIT_START;
    _OS_STACKS_CORE1_VAR_ALL_END = _OS_STACKS_CORE1_VAR_NOINIT_END;
    _OS_STACKS_CORE1_VAR_ALL_LIMIT = _OS_STACKS_CORE1_VAR_NOINIT_LIMIT;
  }

  .OS_STACKS_CORE2_VAR_NOINIT :
  {
    _OS_STACKS_CORE2_VAR_NOINIT_START = .;
    _OS_STACKS_CORE2_VAR_NOINIT_END = . - 1;
    _OS_STACKS_CORE2_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_STACKS_CORE2_VAR_LABELS :
  {
    _OS_STACKS_CORE2_VAR_ALL_START = _OS_STACKS_CORE2_VAR_NOINIT_START;
    _OS_STACKS_CORE2_VAR_ALL_END = _OS_STACKS_CORE2_VAR_NOINIT_END;
    _OS_STACKS_CORE2_VAR_ALL_LIMIT = _OS_STACKS_CORE2_VAR_NOINIT_LIMIT;
  }

  .OS_STACKS_CORE3_VAR_NOINIT :
  {
    _OS_STACKS_CORE3_VAR_NOINIT_START = .;
    _OS_STACKS_CORE3_VAR_NOINIT_END = . - 1;
    _OS_STACKS_CORE3_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_STACKS_CORE3_VAR_LABELS :
  {
    _OS_STACKS_CORE3_VAR_ALL_START = _OS_STACKS_CORE3_VAR_NOINIT_START;
    _OS_STACKS_CORE3_VAR_ALL_END = _OS_STACKS_CORE3_VAR_NOINIT_END;
    _OS_STACKS_CORE3_VAR_ALL_LIMIT = _OS_STACKS_CORE3_VAR_NOINIT_LIMIT;
  }

  .OS_STACKS_CORE4_VAR_NOINIT :
  {
    _OS_STACKS_CORE4_VAR_NOINIT_START = .;
    _OS_STACKS_CORE4_VAR_NOINIT_END = . - 1;
    _OS_STACKS_CORE4_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_STACKS_CORE4_VAR_LABELS :
  {
    _OS_STACKS_CORE4_VAR_ALL_START = _OS_STACKS_CORE4_VAR_NOINIT_START;
    _OS_STACKS_CORE4_VAR_ALL_END = _OS_STACKS_CORE4_VAR_NOINIT_END;
    _OS_STACKS_CORE4_VAR_ALL_LIMIT = _OS_STACKS_CORE4_VAR_NOINIT_LIMIT;
  }

  .OS_STACKS_CORE5_VAR_NOINIT :
  {
    _OS_STACKS_CORE5_VAR_NOINIT_START = .;
    _OS_STACKS_CORE5_VAR_NOINIT_END = . - 1;
    _OS_STACKS_CORE5_VAR_NOINIT_LIMIT = .;
  } > DDR0

  .OS_STACKS_CORE5_VAR_LABELS :
  {
    _OS_STACKS_CORE5_VAR_ALL_START = _OS_STACKS_CORE5_VAR_NOINIT_START;
    _OS_STACKS_CORE5_VAR_ALL_END = _OS_STACKS_CORE5_VAR_NOINIT_END;
    _OS_STACKS_CORE5_VAR_ALL_LIMIT = _OS_STACKS_CORE5_VAR_NOINIT_LIMIT;
  }

  .OS_USER_CODE :
  {
    _OS_USER_CODE_START = .;
    *(.OS_Can_30_McanIsr_0_CODE)
    *(.OS_Default_BSW_Async_Task_Core0_CODE)
    *(.OS_Default_BSW_Sync_Task_CODE)
    *(.OS_Default_Init_Task_CODE)
    *(.OS_Default_Init_Task_Trusted_CODE)
    *(.OS_Default_RTE_Mode_switch_Task_CODE)
    *(.OS_ERRORHOOK_CODE)
    *(.OS_LinIsr_0_CODE)
    *(.OS_StartApplication_Appl_Init_Task_CODE)
    *(.OS_StartApplication_Appl_Task_Core0_CODE)
    *(.OS_XSignalIsr_OsCore0_CODE)
    _OS_USER_CODE_END = . - 1;
    _OS_USER_CODE_LIMIT = .;
  } > DDR0

  .OS_USER_CODE_LABELS :
  {
    _OS_USER_CODE_ALL_START = _OS_USER_CODE_START;
    _OS_USER_CODE_ALL_END = _OS_USER_CODE_END;
    _OS_USER_CODE_ALL_LIMIT = _OS_USER_CODE_LIMIT;
  }

  .OS_USER_CONST :
  {
    _OS_USER_CONST_START = .;
    *(.OS_OsApplication_Trusted_Core0_CONST)
    _OS_USER_CONST_END = . - 1;
    _OS_USER_CONST_LIMIT = .;
  } > DDR0

  .OS_USER_CONST_LABELS :
  {
    _OS_USER_CONST_ALL_START = _OS_USER_CONST_START;
    _OS_USER_CONST_ALL_END = _OS_USER_CONST_END;
    _OS_USER_CONST_ALL_LIMIT = _OS_USER_CONST_LIMIT;
  }

  .R5F_Startup_Code : ALIGN(4)
  {
    _R5F_Startup_Code_START = .;
    *(.startupCode)
    _R5F_Startup_Code_END = . - 1;
    _R5F_Startup_Code_LIMIT = .;
  } > OCMCRAM_Common

  .R5F_Startup_Code_LABELS :
  {
    _R5F_Startup_Code_ALL_START = _R5F_Startup_Code_START;
    _R5F_Startup_Code_ALL_END = _R5F_Startup_Code_END;
    _R5F_Startup_Code_ALL_LIMIT = _R5F_Startup_Code_LIMIT;
  }

  .R5F_Startup_Data : ALIGN(4)
  {
    _R5F_Startup_Data_START = .;
    *(.startupData)
    _R5F_Startup_Data_END = . - 1;
    _R5F_Startup_Data_LIMIT = .;
  } > OCMCRAM_Common

  .R5F_Startup_Data_LABELS :
  {
    _R5F_Startup_Data_ALL_START = _R5F_Startup_Data_START;
    _R5F_Startup_Data_ALL_END = _R5F_Startup_Data_END;
    _R5F_Startup_Data_ALL_LIMIT = _R5F_Startup_Data_LIMIT;
  }

  .STACK_C0 : ALIGN(4)
  {
    _STACK_C0_START = .;
    . += 1024;
    . = ALIGN(4);
    _STACK_C0_END = . - 1;
    _STACK_C0_LIMIT = .;
  } > OCMCRAM_Common

  .STACK_C0_LABELS :
  {
    _STACK_C0_ALL_START = _STACK_C0_START;
    _STACK_C0_ALL_END = _STACK_C0_END;
    _STACK_C0_ALL_LIMIT = _STACK_C0_LIMIT;
  }

  .STACK_C1 : ALIGN(4)
  {
    _STACK_C1_START = .;
    . += 1024;
    . = ALIGN(4);
    _STACK_C1_END = . - 1;
    _STACK_C1_LIMIT = .;
  } > OCMCRAM_Common

  .STACK_C1_LABELS :
  {
    _STACK_C1_ALL_START = _STACK_C1_START;
    _STACK_C1_ALL_END = _STACK_C1_END;
    _STACK_C1_ALL_LIMIT = _STACK_C1_LIMIT;
  }

  .STACK_C2 : ALIGN(4)
  {
    _STACK_C2_START = .;
    . += 1024;
    . = ALIGN(4);
    _STACK_C2_END = . - 1;
    _STACK_C2_LIMIT = .;
  } > OCMCRAM_Common

  .STACK_C2_LABELS :
  {
    _STACK_C2_ALL_START = _STACK_C2_START;
    _STACK_C2_ALL_END = _STACK_C2_END;
    _STACK_C2_ALL_LIMIT = _STACK_C2_LIMIT;
  }

  .STACK_C3 : ALIGN(4)
  {
    _STACK_C3_START = .;
    . += 1024;
    . = ALIGN(4);
    _STACK_C3_END = . - 1;
    _STACK_C3_LIMIT = .;
  } > OCMCRAM_Common

  .STACK_C3_LABELS :
  {
    _STACK_C3_ALL_START = _STACK_C3_START;
    _STACK_C3_ALL_END = _STACK_C3_END;
    _STACK_C3_ALL_LIMIT = _STACK_C3_LIMIT;
  }

  .STACK_C4 : ALIGN(4)
  {
    _STACK_C4_START = .;
    . += 1024;
    . = ALIGN(4);
    _STACK_C4_END = . - 1;
    _STACK_C4_LIMIT = .;
  } > OCMCRAM_Common

  .STACK_C4_LABELS :
  {
    _STACK_C4_ALL_START = _STACK_C4_START;
    _STACK_C4_ALL_END = _STACK_C4_END;
    _STACK_C4_ALL_LIMIT = _STACK_C4_LIMIT;
  }

  .STACK_C5 : ALIGN(4)
  {
    _STACK_C5_START = .;
    . += 1024;
    . = ALIGN(4);
    _STACK_C5_END = . - 1;
    _STACK_C5_LIMIT = .;
  } > OCMCRAM_Common

  .STACK_C5_LABELS :
  {
    _STACK_C5_ALL_START = _STACK_C5_START;
    _STACK_C5_ALL_END = _STACK_C5_END;
    _STACK_C5_ALL_LIMIT = _STACK_C5_LIMIT;
  }

  .Startup_Code : ALIGN(4)
  {
    _Startup_Code_START = .;
    *(.brsStartup)
    _Startup_Code_END = . - 1;
    _Startup_Code_LIMIT = .;
  } > OCMCRAM_Common

  .Startup_Code_LABELS :
  {
    _Startup_Code_ALL_START = _Startup_Code_START;
    _Startup_Code_ALL_END = _Startup_Code_END;
    _Startup_Code_ALL_LIMIT = _Startup_Code_LIMIT;
  }

  .Startup_Labels :
  {
    _RESET = brsStartupEntry;
    _start = brsStartupEntry;
    _start_c1 = brsStartupEntry;
    _start_c2 = brsStartupEntry;
    _start_c3 = brsStartupEntry;
    _start_c4 = brsStartupEntry;
    _start_c5 = brsStartupEntry;
    _brsStartupEntry = brsStartupEntry;
  }

  .Startup_Stack_Symbols :
  {
    __section_stack_c0_end = _STACK_C0_LIMIT;
    __section_stack_c1_end = _STACK_C1_LIMIT;
    __section_stack_c2_end = _STACK_C2_LIMIT;
    __section_stack_c3_end = _STACK_C3_LIMIT;
    __section_stack_c4_end = _STACK_C4_LIMIT;
    __section_stack_c5_end = _STACK_C5_LIMIT;
  }

  .TI_sysfw_sections_bss_devgroup : ALIGN(4)
  {
    _TI_sysfw_sections_bss_devgroup_START = .;
    *(.boardcfg_data)
    *(.data_user)
    *(.bss.devgroup.DMSC_INTERNAL)
    *(.bss.devgroup.MAIN)
    *(.bss.devgroup.MCU_WAKEUP)
    . = ALIGN(4);
    _TI_sysfw_sections_bss_devgroup_END = . - 1;
    _TI_sysfw_sections_bss_devgroup_LIMIT = .;
  } > DDR0

  .TI_sysfw_sections_bss_devgroup_LABELS :
  {
    _TI_sysfw_sections_bss_devgroup_ALL_START = _TI_sysfw_sections_bss_devgroup_START;
    _TI_sysfw_sections_bss_devgroup_ALL_END = _TI_sysfw_sections_bss_devgroup_END;
    _TI_sysfw_sections_bss_devgroup_ALL_LIMIT = _TI_sysfw_sections_bss_devgroup_LIMIT;
  }

  .TI_sysfw_sections_const_devgroup : ALIGN(4)
  {
    _TI_sysfw_sections_const_devgroup_START = .;
    *(.const.devgroup.DMSC_INTERNAL)
    *(.const.devgroup.MAIN)
    *(.const.devgroup.MCU_WAKEUP)
    . = ALIGN(4);
    _TI_sysfw_sections_const_devgroup_END = . - 1;
    _TI_sysfw_sections_const_devgroup_LIMIT = .;
  } > DDR0

  .TI_sysfw_sections_const_devgroup_LABELS :
  {
    _TI_sysfw_sections_const_devgroup_ALL_START = _TI_sysfw_sections_const_devgroup_START;
    _TI_sysfw_sections_const_devgroup_ALL_END = _TI_sysfw_sections_const_devgroup_END;
    _TI_sysfw_sections_const_devgroup_ALL_LIMIT = _TI_sysfw_sections_const_devgroup_LIMIT;
  }

  .OS_CODE :
  {
    _OS_CODE_START = .;
    *(.OS_CODE)
    *(.OS_OS_COREINITHOOK_CODE)
    _OS_CODE_END = . - 1;
    _OS_CODE_LIMIT = .;
  } > DDR0

  .OS_CODE_LABELS :
  {
    _OS_CODE_ALL_START = _OS_CODE_START;
    _OS_CODE_ALL_END = _OS_CODE_END;
    _OS_CODE_ALL_LIMIT = _OS_CODE_LIMIT;
  }

  .OS_CONST :
  {
    _OS_CONST_START = .;
    *(.OS_CONST)
    *(.OS_CORE0_CONST)
    *(.OS_SystemApplication_OsCore0_CONST)
    _OS_CONST_END = . - 1;
    _OS_CONST_LIMIT = .;
  } > DDR0

  .OS_CONST_LABELS :
  {
    _OS_CONST_ALL_START = _OS_CONST_START;
    _OS_CONST_ALL_END = _OS_CONST_END;
    _OS_CONST_ALL_LIMIT = _OS_CONST_LIMIT;
  }

  .rodata :
  {
    _rodata_START = .;
    *(.const)
    _rodata_END = . - 1;
    _rodata_LIMIT = .;
  } > DDR0

  .text :
  {
    _text_START = .;
    *(.text)
    _text_END = . - 1;
    _text_LIMIT = .;
  } > DDR0

  .Const_Default_LABELS :
  {
    _Const_Default_ALL_START = _rodata_START;
    _Const_Default_ALL_END = _text_END;
    _Const_Default_ALL_LIMIT = _text_LIMIT;
  }

  .bss : ALIGN(4)
  {
    _bss_START = .;
    *(.bss)
    *(.heap)
    *(.stack)
    . = ALIGN(4);
    _bss_END = . - 1;
    _bss_LIMIT = .;
  } > DDR0

  .data : ALIGN(4)
  {
    _data_START = .;
    *(.data)
    . = ALIGN(4);
    _data_END = . - 1;
    _data_LIMIT = .;
  } > DDR0, RUN > DDR0,
  LOAD_START(_data_ROM_START),
  LOAD_END(_data_ROM_LIMIT)

  .Data_Default_LABELS :
  {
    _Data_Default_ALL_START = _bss_START;
    _Data_Default_ALL_END = _data_END;
    _Data_Default_ALL_LIMIT = _data_LIMIT;
  }

}

Hi Tomislav,

Let me look into this further and get back to you tomorrow.

Thanks,

Neehar

Hi Tomislav,

Tomislav Zivec said:

Now I am able to reach main( in debugger but when target is run eventually it jumps to 0x4 address and from there to 0x0. Do you know what could be the issue?

Have you stepped through the code to see when the jump to address 0x4 happens?

Tomislav Zivec said:

Could you crosscheck if all the dependencies are correctly placed for MCU_R5_0 core?

Let me check this for you.

Thanks,

Neehar

Hello Neehar,

I have an important update, I disabled compilation optimization -O3 flag to -O0 and did some smaller Os changes and now the AUTOSAR stack is reaching the tasks but only one time. I am having issue with Os SystemTimer which is connected to MCU_TIMER0. Seems like it is running and setting MATCH flag in the IRQ STATUS register and it is pending and the flag is on correct location in the Interrupt Router so Os should be able to see it but the problem is IRQ is not triggering ISR routine. Can you please advise what to check and debugging issue today because our delivery to clinet is blocked at this point and need to debug it ASAP. Is there a possibility also that XDS110 USB probe is preventing it to service interrupts?

Can you please take this with highest priority and can perhaps today live debugging session be done from your side with me?

Thank you & hope to hear from you soon.

Tomislav

Hi Tomislav,

I am looping in our Autosar expert who will be able to assist better regarding your issues.

Thanks,

Neehar

Hello Tomislav,

There are multiple points i want to tell you here.

Tomislav Zivec said:

I have installed CCS9.3 and didn't make a change. But what did make a change is setting loadSciserverFlag to 0 in launch.js file. I believe the problem was SciServer was loaded there and then since I want my AUTOSAR application to run on it it failed during overwrite.

sciserver will be loaded in MCU1_0 core but not in any other cores. It should always run.

Tomislav Zivec said:

Now I am able to reach main( in debugger but when target is run eventually it jumps to 0x4 address and from there to 0x0. Do you know what could be the issue?

In the screenshot , only 3 cores are showing MCU1_0,MCU1_1 and M3 core .May i know why ?

Tomislav Zivec said:

I am trying to flash mine AUTOSAR build application to MCU2_1 with jacinto v7.2.0.6 PSDK.

You were mentioning MCU2_1 core to use in AUTOSAR which means MAIN_R5_0_1 but also again you are also saying MCU1_0 caused an issue .May i 

Please know what core you need to run AUTOSAR application ?

Tomislav Zivec said:

reaching the tasks but only one time. I am having issue with Os SystemTimer which is connected to MCU_TIMER0. Seems like it is running and setting MATCH flag in the IRQ STATUS register and it is pending and the flag is on correct location in the Interrupt Router so Os should be able to see it but the problem is IRQ is not triggering ISR routine.

Sciserver should always keep running irrespective of any application on any cores.If this is not running then all the sciclient calls will fail , one of the call is this interrupt router call.

Along with it , what is your boot sequence and boot media ?

Tomislav Zivec said:

Can you please take this with highest priority and can perhaps today live debugging session be done from your side with me?

I am fully occupied this week with pre-scheduled meetings, we can have it around next week.

Regards

Tarun Mukesh

Hello Mr. Puvvada,

Nice to talk to you again.

Thank you for the update i will try to clarify things, it might come messay since the start and trying out different options.

Tarun Mukesh Puvvada said:

sciserver will be loaded in MCU1_0 core but not in any other cores. It should always run.

Okay, but then why do I have to set this flag to not load it on MCU1_0?

Tarun Mukesh Puvvada said:

In the screenshot , only 3 cores are showing MCU1_0,MCU1_1 and M3 core .May i know why ?

Sure, the point is I have set up Target Configuration like that in CCS just not to have 20 cores and what else that I am not interested in. This 3 are my main focus since I trigger lanuch.js and it should what it has to before I program to MCU1_0. Is that a problem if I don't have whole list there?

Tarun Mukesh Puvvada said:

You were mentioning MCU2_1 core to use in AUTOSAR which means MAIN_R5_0_1 but also again you are also saying MCU1_0 caused an issue .May i 

Please know what core you need to run AUTOSAR application ?

Great question. So at first I thought to run it on MAIN MCU2_1 but since Vector created StartApplication for MCU MCU1_0 core than I switched to it and working with that one. So Application should run on MCU1_0.

Tarun Mukesh Puvvada said:

Sciserver should always keep running irrespective of any application on any cores.If this is not running then all the sciclient calls will fail , one of the call is this interrupt router call.

How can I verify I have everything needed for it to work and that Interrupt Router is able to use it?

Tarun Mukesh Puvvada said:

I am fully occupied this week with pre-scheduled meetings, we can have it around next week.

Thank you for the effort anyway, well maybe you can support me on this ticket at least because next week it will be I am afraid too late for us since the issue has been escalated on both internal and clients side. Lot of Stakeholders involved in this.

I would appreciate if you have any suggestions what to check just to try to narrow it down.

Thank you & Best Regards,

Tomislav

Hello,

Yes i can support via this ticket as well.

Tomislav Zivec said:

Great question. So at first I thought to run it on MAIN MCU2_1 but since Vector created StartApplication for MCU MCU1_0 core than I switched to it and working with that one. So Application should run on MCU1_0.

Thanks for the details .If the core is MCU1_0 then it is a DM core so you need to follow the below pdf for sci server integration if it is VECTOR AUTOSAR OS

https://www.ti.com/lit/an/spracy6/spracy6.pdf

May i know have you done this ?

Tomislav Zivec said:

I am having issue with Os SystemTimer which is connected to MCU_TIMER0. Seems like it is running and setting MATCH flag in the IRQ STATUS register and it is pending and the flag is on correct location in the Interrupt Router so Os should be able to see it but the problem is IRQ is not triggering ISR routine.

Regarding timer interrupt regsitration we have example at /mcusw/mcal_drv/mcal/examples/Gpt/soc/j721e/mcu1_0/GptApp_Startup.c file with below API

Regards

Tarun Mukesh

Thank you Tarun Mukesh,

Tarun Mukesh Puvvada said:

May i know have you done this ?

No, I did not do it since I didn't know about it, thank you for providing the link. Well seems to me SciServer is not being initalized in the Vector code so I am quite interested how that is supposed to work. Also now when reading the provided doc I see it is kinda expected to have SciServer Tasks and trigger Events from DaVinci Developer. Those are also not present. Do you believe they have done it somehow in a different way and that is supposed to work. I am using evaluation SIP from cca 5 year ago and most likely TI has been in the loop for it. Maybe you internally have any information about this cooperation and pecialists that worked on it together with Vector?

Tarun Mukesh Puvvada said:

Regarding timer interrupt regsitration we have example at /mcusw/mcal_drv/mcal/examples/Gpt/soc/j721e/mcu1_0/GptApp_Startup.c file with below API

GptAppStartup_InterruptConfig

Okay that is for the Gpt, but MCU_TIMER0 is used as an Os System Timer and shall not be handled through Gpt or?

Thanks again,

Tomislav

Hello,

Tomislav Zivec said:

Okay that is for the Gpt, but MCU_TIMER0 is used as an Os System Timer and shall not be handled through Gpt or?

If you are not using MCU_TIMER0 via MCAL GPT driver , May i know how you are doing interrupt enabling and routing ?

Tomislav Zivec said:

No, I did not do it since I didn't know about it, thank you for providing the link. Well seems to me SciServer is not being initalized in the Vector code so I am quite interested how that is supposed to work. Also now when reading the provided doc I see it is kinda expected to have SciServer Tasks and trigger Events from DaVinci Developer. Those are also not present. Do you believe they have done it somehow in a different way and that is supposed to work. I am using evaluation SIP from cca 5 year ago and most likely TI has been in the loop for it. Maybe you internally have any information about this cooperation and pecialists that worked on it together with Vector?

5 years ago is a pretty long time and i can check if any one have information on this. Sciserver is definitely needed on MCU1_0 core since it is a DM core.

The PDF i have shared also states " The content covered is applicable for systems running AUTOSAR on MCU R5F with SDK7.1 or later." 

Regards

Tarun Mukesh

Tarun Mukesh Puvvada said:

If you are not using MCU_TIMER0 via MCAL GPT driver , May i know how you are doing interrupt enabling and routing ?

The Os is handling it.

Tarun Mukesh Puvvada said:

The PDF i have shared also states " The content covered is applicable for systems running AUTOSAR on MCU R5F with SDK7.1 or later." 

yes I can see it, and yes I am using v7.2.

I have an update in debugging:

Scenario 1: I am able to hit ISR for Interrupt 38 (MCU_TIMER0) once every 2 runs because seems that CPU Reset and Restart does not reset peripherals from last run where Os started it. it is happening because __mpu_init enables interrupts before main(), I have put additional clearing of the VIM_IRQVEC by writting something to it before BrsStartupInstSetInit but it does not clear it for some reason even though at that point from the code provided below TIMER0 has been stopped by my assembly code, its IRQ pending flags have been cleared and corresponding R5FSS_VIM_IRQSTS_j has been cleared. But clearing from the Memory Browser works when this 2 prerequisite steps are in that value and then just by writting to VIM_IRQVEC it removes VALID flag from VIM_ACTIRQ register. Seems assembly is not able to do the same.

May I ask why do you have global interrup enable call in the __mpu_init?

Scenario 2: I am getting to Os_IdleTask and stays there with MCU_TIMER0 running, having the IRQ pending flag, also VIM sees it and VIM_ACTIRQ is Valid but it does not trigger interrupt and does not hit ISR for some reason. This happens if I have some breakpoints in the i.e. EcuM_StartupTwo etc but does not happen in the run without breakpoints, I just end up on the address 0x0.

Can you support me why that is happening and possibilities to look at.

Thank you and Best Regards,

Tomislav

Hello,

The definition what TI has provided for __mpu_init in PDK is as follows

__attribute__((section(".startupCode")))  __attribute__((weak)) void __mpu_init(void)
{
    uint32_t loopCnt = 0U, regAddr;
    CSL_ArmR5CPUInfo info;
    uint32_t    maxIntrs;
    CSL_vimRegs     *pRegs;
    CSL_armR5StartupGetCpuID(&info);
#if defined(CSL_MAIN_DOMAIN_VIM_BASE_ADDR0) && defined(CSL_MAIN_DOMAIN_VIM_BASE_ADDR1)
    if (info.grpId == CSL_ARM_R5_CLUSTER_GROUP_ID_0)
    {
        /* MCU SS Pulsar R5 SS */
        regAddr = (info.cpuID == CSL_ARM_R5_CPU_ID_0)?
                                 CSL_MCU_DOMAIN_VIM_BASE_ADDR0:
                                 CSL_MCU_DOMAIN_VIM_BASE_ADDR1;

    }
    else
    {
        /* MAIN SS Pulsar R5 SS */
        regAddr = (info.cpuID == CSL_ARM_R5_CPU_ID_0)?
                                 CSL_MAIN_DOMAIN_VIM_BASE_ADDR0:
                                 CSL_MAIN_DOMAIN_VIM_BASE_ADDR1;

    }
#else
    /* MCU SS Pulsar R5 SS */
    regAddr = (info.cpuID == CSL_ARM_R5_CPU_ID_0)?
                             CSL_MCU_DOMAIN_VIM_BASE_ADDR0:
                             CSL_MCU_DOMAIN_VIM_BASE_ADDR1;
#endif
    pRegs       = (CSL_vimRegs *)(uintptr_t) regAddr;
    maxIntrs    = pRegs->INFO;

#if defined (SOC_AM65XX) || defined (SOC_J721E)
    /* Limit the outstanding transactions to 2
     * only for AM65xx and J721e platforms
     * Later SoCs do not have this issue
     */
    CSL_armR5SetDLFOBit();
#else
    /* Fix for PRSDK-8161
     * For AM64x and J7200, there is no issue of limitting outstanding
     * transactions. R5F core can support full 7 outstanding transactions
     */
#endif
    _enable_mpu();              /* Enable MPU */
    _enable_cache();            /* Enable all caches */
    CSL_armR5StartupFpuEnable( 1 );    /* Enable FPU */
    CSL_armR5StartupIntrEnableVic(1);  /* Enable VIC */
    
    /* Disable/Clear pending Interrupts in VIM before enabling CPU Interrupts */
    /* This is done to prevent serving any bogus interrupt */
    for (loopCnt = 0U ; loopCnt < maxIntrs; loopCnt++)
    {
        /* Disable interrupt in vim */
        CSL_startupVimSetIntrEnable((CSL_vimRegs *)(uintptr_t)regAddr,
                                    loopCnt,
                                    false);
        /* Clear interrupt status */
        CSL_startupVimClrIntrPending((CSL_vimRegs *)(uintptr_t)regAddr,
                                     loopCnt);
    }
    CSL_armR5StartupIntrEnableFiq(1);  /* Enable FIQ */
    CSL_armR5StartupIntrEnableIrq(1);  /* Enable IRQ */
}

The above will be called during startup of the core. I am not sure whether VECTOR is using the same in its Brs startup or not.

In the above API, we will clear and disable all the pending interrupts interrupts in VIM . Then Enable both FIQ and IRQ.

 Later comes vector's os_init if the MPU protection is enabled in AUTOSAR then mpu configuration will again be redone.

Interrupts need to be enabled in mpu init during start up phase since OS can use interrupts  before application main reaches.

Regards

Tarun Mukesh

Hello again,

Yes, I believe they are using the same and I have seen this part of the code, even though it is taken jsut by ti.csl.init.aer5f image so cannot go through it I believe what you do here is correct but didn't account one thing in CCS, when we perfrom Restart or CPU Reset peripherals are not cleared and basically Timer is still running and it will most likely trigger IRQ again before reaching main even though VIM ACTIRQ was cleared.

But anyway..current situation is as follows:

I fixed ISR triggering and now the execution is stable and always leading to same scenario. Timer ISR is getting triggered but only 2 times.

On the second on this line „bx r1“ where R1 is having a correct address of Os_TimerPfrtIsr it results in jump to address 0x8 which is SWI.

If I do step into by assembly it is able to do the jump but then again it fails somewhere inside. Address seem properly alligned and CPU is in ARM mode, no THUMB.

Do you know if it is expected for Os handling to raise SWI and gets stuck there? Should it be serviced somehow or it is just some bug? Not sure why it doesnt happen on the ISR Interrupt_38(MCU_TIMER0) but on second one it does...

Can you help me narrow it somehow?

Best Regards,

Tomislav

Hello,

Tomislav Zivec said:

through it I believe what you do here is correct but didn't account one thing in CCS, when we perfrom Restart or CPU Reset peripherals are not cleared and basically Timer is still running and it will most likely trigger IRQ again before reaching main even though VIM ACTIRQ was cleared.

Reset of core or CPU doesn't turn off peripherals its the system reset which turns peripherals OFF.

so yes timer will keep running in the background and continue raising interrupts.

Tomislav Zivec said:

Do you know if it is expected for Os handling to raise SWI and gets stuck there? Should it be serviced somehow or it is just some bug? Not sure why it doesnt happen on the ISR Interrupt_38(MCU_TIMER0) but on second one it does...

The points you are raising more into OS handling and it would be good to ask vector about this rather than TI. TI is not aware of internal MICROSAR calls.From MCU_TIMER point of view it will keep raising interrupt as per time configured , interrupt registration and isr handling .

Regards

Tarun Mukesh