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TDA4AH-Q1: Required to follow Power-Down sequence?

Trevor Fox
Intellectual 550 points

Part Number: TDA4AH-Q1

Tool/software:

Hi

I am designing a custom Circuit card that uses the Jacinto processor. For this application - we may be getting power shut down without notice and would not have time to always follow the recommended power-down sequencing as in the data sheet. 

Since the whole board is powering down, and there is no expectation that the part will be used again until full power is restored - is there any reason that I have to follow this recommended power down? What would happen if I don't?

I will always be following the Power-Up sequencing as per data sheet.

Thanks

  • +1
    TI__Guru 57645 points

    The key parameter is that MCU_PORz and PORz must be asserted low for 200us (minimum) to ensure the SOC resources enter into safe state before any voltage begins to ramp down.  Once this is done, the power down sequence is not as critical and simultaneous rail ramp down will not damage the device.