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c6678 SL2 questions

Aamir Husain
Expert 2715 points

Can one make use of the IDMA engine to transfer data from the 4M shared SL2 and the 512K individual core L2? I am venturing not as it is not local to the corePac. However, code in SL2 caches in L1P.

Generally speaking, is the interaction between L2 and L1P/L1D the same as the interaction between SL2 and L1P/L1D?

Whay about Error correction and detection, does that work for the 4M shared L2 or is that just for L2/L1P etc? What kind of speed impact does enabling this EDC capability have on the performance generally speaking?

thanks,

Aamir

  • 0
    TI__Mastermind 30825 points

    Aamir,

    IDMA can only access memories within a CorePac itself.  The Multicore Shared Memory (MSMC Memory) - Shared L2/L3 is outside of the core and you cannot use IDMA to access it. You'll want to use EDMA, QDMA or even the Multicore Navigator for these transfers.

    The MSMC Memory (Shared L2/L3) does support EDC, please see the Multicore Shared Memory Controller UG - SPRUGW7 for details on it's use and implementation.

    Enabling EDC has no speed/performance impact.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Expert 2715 points

    Chad,

    Thanks for your earlier answers.

    Is there any example code that comes with the EVM or CCSv.5 in the directory hierarchy that shows the EDC usage?

    The MSMC scrubbing engine is mentioned as running in the background. That to me seems to imply no performance impact yet on page 2-16 of the user guide it talks of a negative performance impact. Can you explain that. Maybe I misunderstand the feature. Also in section 2.5.4, it talks of  scrubbing cycles and scrub bursts. Can you define what each is? The explanation in the user guide seems quite confusing

    Again is there any example code that shows the use of the scrubbing engine?

    Is the primary use of the EDC to handle bit errors due to bitflips due to radiation in SRAM memory etc.

    When one talks of stats in the SMNCEA register, why would one be concerned with the saturatation logic, as just one non-corrrectable error in code would be sufficient for the DSP to crash if it got exercised or is this more for data. I would think that when the interrupt occurs on this particular condition happening, the routine could trigger an exception in the DSP.

    Thanks, Aamir

  • 0 in reply to Aamir Husain
    TI__Mastermind 30825 points

    Aamir,

    I don't believe there is any particular code examples for this.  It's primarily set the registers and it does the rest.

    The MSMC scrubbing engine can have some small impact on a heavily used MSMC.  Sorry for the confusion, I thought you where specifically talking about when EDC functionality was in use and was not taking into account the MSMC scrubbing.  I don't have specific details on the performance impact but it should be minimal. I'll try to get more details.

    The primary purpose of the EDC is to handle bit flips do to Soft Error's which can be induced by alpha and beta particle radiation.  The ever increasing shrinking of the gate sizes of transistors make devices more prone to the probability of this occurring.  Other things are done to counteract this in processes but a secondary protection mechanism such as EDC are still needed.

    The SMNCEA register is potentially useful if the corruption of it does not have the potential to result in a catastrophic failure.  You're correct that if it's in code, and executed it could result in a catastrophic failure.  However if it's a data section who's bit flip will not result in a failure, then it may be ignored or the data may be reloaded, that depends on the developer.  This would be processed by an Interrupt/Exception handler routine based on the generated event.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Expert 2715 points

    Chad Courtney wrote the following post at 01-09-2012 8:43 AM:

    Aamir,

    I don't believe there is any particular code examples for this.  It's primarily set the registers and it does the rest.

    ok!

    The MSMC scrubbing engine can have some small impact on a heavily used MSMC.  Sorry for the confusion, I thought you where specifically talking about when EDC functionality was in use and was not taking into account the MSMC scrubbing.  I don't have specific details on the performance impact but it should be minimal. I'll try to get more details.

    Okay I gather the impact is probably minimal but you will provide me with more details later - thanks. As most writes to MSMC or L2 are probably not aligned to 32 bytes it would appear to me that the scrubbing engine is needed practically always otherwise lots of invalid parity and hence no effective EDC. Our intent is for all code to sit in MSMC L2 and each of the 8 cores to access different portions of it depending on the application so we probably need scrubbing on and also expect that the MSMC is heavily used.

    Is the scrubbing burst going through the complete MSMC or corePac L2 memory? Also, in the MSMC document it talks of the cycle spacing between each series of burst as being set by REFDEL and talking on a value of (1 to 255) x 1024. What about the time between each 32 byte memory location scrubbing? Is that configurable? and how much time does it take to scrub the entire memory in relation to the REFDEL setting time between each start of the scrub burst?

    The primary purpose of the EDC is to handle bit flips do to Soft Error's which can be induced by alpha and beta particle radiation.  The ever increasing shrinking of the gate sizes of transistors make devices more prone to the probability of this occurring.  Other things are done to counteract this in processes but a secondary protection mechanism such as EDC are still needed.

    The SMNCEA register is potentially useful if the corruption of it does not have the potential to result in a catastrophic failure.  You're correct that if it's in code, and executed it could result in a catastrophic failure.  However if it's a data section who's bit flip will not result in a failure, then it may be ignored or the data may be reloaded, that depends on the developer.  This would be processed by an Interrupt/Exception handler routine based on the generated event.

    thanks

    Aamir