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[FAQ] J784S4XEVM: CLK-DATA and DEV-DATA for enabling UARTs

Gokul Praveen
Genius 11020 points
Part Number: J784S4XEVM

Tool/software:

Can you provide the clk-data and dev-data for the different UARTs across different boards?

  • +1
    TI__Genius 11020 points

    The below changes have to be applied irrespective of whichever board it is :

     [FAQ] TDA4VM: J721e:/J7200: How to switch console to a different UART instance 

    =====================

    Board-Specific changes

    ====================

    J721S2( MAIN_UART 2,5,8)
    =======

    • WKUP UART
      • https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/1754.enable_5F00_wkupuart_5F00_j721s2.patch
    • MAIN UART2 
      • From 6604155a3e34eb2a208164f601992bc6a5b21f93 Mon Sep 17 00:00:00 2001
From: Gokul Praveen <g-praveen@ti.com>
Date: Thu, 11 Sep 2025 17:08:34 +0530
Subject: [PATCH] mainuart2_j721s2

---
 output/j721s2/spl-hsm/clk-data.c | 3 +++
 output/j721s2/spl-hsm/dev-data.c | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/output/j721s2/spl-hsm/clk-data.c b/output/j721s2/spl-hsm/clk-data.c
index 9b08b33..1796e4c 100644
--- a/output/j721s2/spl-hsm/clk-data.c
+++ b/output/j721s2/spl-hsm/clk-data.c
@@ -270,6 +270,7 @@ static const struct clk_data clk_list[] = {
 	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0, 48000000),
 	CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
 	CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0),
+	CLK_DIV("usart_programmable_clock_divider_out2", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c8, 0, 2, 0, 0),
 };
 
 static const struct dev_clk soc_dev_clk_data[] = {
@@ -388,6 +389,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(360, 22, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(360, 23, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(360, 25, "board_0_tck_out"),
+	DEV_CLK(351, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(351, 3, "usart_programmable_clock_divider_out2"),
 };
 
 const struct ti_k3_clk_platdata j721s2_clk_platdata = {
diff --git a/output/j721s2/spl-hsm/dev-data.c b/output/j721s2/spl-hsm/dev-data.c
index 9986318..7b1d82e 100644
--- a/output/j721s2/spl-hsm/dev-data.c
+++ b/output/j721s2/spl-hsm/dev-data.c
@@ -44,6 +44,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
 	[16] = PSC_LPSC(78, &soc_psc_list[1], &soc_pd_list[3], NULL),
 	[17] = PSC_LPSC(80, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[16]),
 	[18] = PSC_LPSC(81, &soc_psc_list[1], &soc_pd_list[5], &soc_lpsc_list[16]),
+	[19] = PSC_LPSC(44, &soc_psc_list[1], &soc_pd_list[2], NULL),
 };
 
 static struct ti_dev soc_dev_list[] = {
@@ -71,6 +72,7 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(4, &soc_lpsc_list[16]),
 	PSC_DEV(202, &soc_lpsc_list[17]),
 	PSC_DEV(203, &soc_lpsc_list[18]),
+	PSC_DEV(351, &soc_lpsc_list[19]),
 };
 
 const struct ti_k3_pd_platdata j721s2_pd_platdata = {
-- 
2.34.1
    • MAIN UART 5 
      • From 30d4cfa54a67015e0c0553374688207a402a16ca Mon Sep 17 00:00:00 2001
From: Gokul Praveen <g-praveen@ti.com>
Date: Thu, 11 Sep 2025 17:17:08 +0530
Subject: [PATCH] mainuart5_j721s2

---
 output/j721s2/spl-hsm/clk-data.c | 3 +++
 output/j721s2/spl-hsm/dev-data.c | 1 +
 2 files changed, 4 insertions(+)

diff --git a/output/j721s2/spl-hsm/clk-data.c b/output/j721s2/spl-hsm/clk-data.c
index 9b08b33..8c8655a 100644
--- a/output/j721s2/spl-hsm/clk-data.c
+++ b/output/j721s2/spl-hsm/clk-data.c
@@ -270,6 +270,7 @@ static const struct clk_data clk_list[] = {
 	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0, 48000000),
 	CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
 	CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0),
+	CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0),
 };
 
 static const struct dev_clk soc_dev_clk_data[] = {
@@ -388,6 +389,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(360, 22, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(360, 23, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(360, 25, "board_0_tck_out"),
+	DEV_CLK(354, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(354, 3, "usart_programmable_clock_divider_out5"),
 };
 
 const struct ti_k3_clk_platdata j721s2_clk_platdata = {
diff --git a/output/j721s2/spl-hsm/dev-data.c b/output/j721s2/spl-hsm/dev-data.c
index 9986318..1425b71 100644
--- a/output/j721s2/spl-hsm/dev-data.c
+++ b/output/j721s2/spl-hsm/dev-data.c
@@ -71,6 +71,7 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(4, &soc_lpsc_list[16]),
 	PSC_DEV(202, &soc_lpsc_list[17]),
 	PSC_DEV(203, &soc_lpsc_list[18]),
+	PSC_DEV(354, &soc_lpsc_list[15]),
 };
 
 const struct ti_k3_pd_platdata j721s2_pd_platdata = {
-- 
2.34.1

    J784S4(MAIN UART 2,3,5.8)
    =======

    • WKUP UART
      • https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/1754.wkup_5F00_uart_5F00_enable_5F00_j784s4.patch
    • MAIN UART 3 
      • From 129b674a6c6f7041ae94ff3305f43457bc51c485 Mon Sep 17 00:00:00 2001
From: Gokul Praveen <g-praveen@ti.com>
Date: Thu, 11 Sep 2025 15:19:25 +0530
Subject: [PATCH] enableuart3_j784s4

---
 output/j784s4/spl-hsm/clk-data.c | 3 +++
 output/j784s4/spl-hsm/dev-data.c | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/output/j784s4/spl-hsm/clk-data.c b/output/j784s4/spl-hsm/clk-data.c
index 6a9239c..bff40f8 100644
--- a/output/j784s4/spl-hsm/clk-data.c
+++ b/output/j784s4/spl-hsm/clk-data.c
@@ -286,6 +286,7 @@ static const struct clk_data clk_list[] = {
 	CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0),
 	CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
 	CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0),
+CLK_DIV("usart_programmable_clock_divider_out3", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081cc, 0, 2, 0, 0),
 };
 
 static const struct dev_clk soc_dev_clk_data[] = {
@@ -415,6 +416,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(398, 22, "gluelogic_hfosc0_clkout"),
 	DEV_CLK(398, 23, "board_0_hfosc1_clk_out"),
 	DEV_CLK(398, 28, "board_0_tck_out"),
+	DEV_CLK(390, 0, "usart_programmable_clock_divider_out3"),
+	DEV_CLK(390, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 };
 
 const struct ti_k3_clk_platdata j784s4_clk_platdata = {
diff --git a/output/j784s4/spl-hsm/dev-data.c b/output/j784s4/spl-hsm/dev-data.c
index f531258..1ea692f 100644
--- a/output/j784s4/spl-hsm/dev-data.c
+++ b/output/j784s4/spl-hsm/dev-data.c
@@ -51,6 +51,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
 	[20] = PSC_LPSC(81, &soc_psc_list[2], &soc_pd_list[6], &soc_lpsc_list[18]),
 	[21] = PSC_LPSC(120, &soc_psc_list[2], &soc_pd_list[7], &soc_lpsc_list[22]),
 	[22] = PSC_LPSC(121, &soc_psc_list[2], &soc_pd_list[7], NULL),
+	[23] = PSC_LPSC(44, &soc_psc_list[2], &soc_pd_list[3], NULL),
 };
 
 static struct ti_dev soc_dev_list[] = {
@@ -82,6 +83,7 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(203, &soc_lpsc_list[20]),
 	PSC_DEV(133, &soc_lpsc_list[21]),
 	PSC_DEV(193, &soc_lpsc_list[22]),
+	PSC_DEV(390, &soc_lpsc_list[23]),
 };
 
 const struct ti_k3_pd_platdata j784s4_pd_platdata = {
-- 
2.34.1
    • MAIN UART 2 
      • From ce16f69d39a8a7cf17cd507e96de28690f904e4b Mon Sep 17 00:00:00 2001
From: Gokul Praveen <g-praveen@ti.com>
Date: Thu, 11 Sep 2025 15:50:57 +0530
Subject: [PATCH] mainuart2_j784s4

---
 output/j784s4/spl-hsm/clk-data.c | 3 +++
 output/j784s4/spl-hsm/dev-data.c | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/output/j784s4/spl-hsm/clk-data.c b/output/j784s4/spl-hsm/clk-data.c
index 6a9239c..19e7efe 100644
--- a/output/j784s4/spl-hsm/clk-data.c
+++ b/output/j784s4/spl-hsm/clk-data.c
@@ -286,6 +286,7 @@ static const struct clk_data clk_list[] = {
 	CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0),
 	CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
 	CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0),
+	CLK_DIV("usart_programmable_clock_divider_out2", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c8, 0, 2, 0, 0),
 };
 
 static const struct dev_clk soc_dev_clk_data[] = {
@@ -415,6 +416,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(398, 22, "gluelogic_hfosc0_clkout"),
 	DEV_CLK(398, 23, "board_0_hfosc1_clk_out"),
 	DEV_CLK(398, 28, "board_0_tck_out"),
+	DEV_CLK(389, 0, "usart_programmable_clock_divider_out2"),
+	DEV_CLK(389, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 };
 
 const struct ti_k3_clk_platdata j784s4_clk_platdata = {
diff --git a/output/j784s4/spl-hsm/dev-data.c b/output/j784s4/spl-hsm/dev-data.c
index f531258..e7965e1 100644
--- a/output/j784s4/spl-hsm/dev-data.c
+++ b/output/j784s4/spl-hsm/dev-data.c
@@ -51,6 +51,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
 	[20] = PSC_LPSC(81, &soc_psc_list[2], &soc_pd_list[6], &soc_lpsc_list[18]),
 	[21] = PSC_LPSC(120, &soc_psc_list[2], &soc_pd_list[7], &soc_lpsc_list[22]),
 	[22] = PSC_LPSC(121, &soc_psc_list[2], &soc_pd_list[7], NULL),
+	[23] = PSC_LPSC(44, &soc_psc_list[2], &soc_pd_list[3], NULL),
 };
 
 static struct ti_dev soc_dev_list[] = {
@@ -82,6 +83,7 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(203, &soc_lpsc_list[20]),
 	PSC_DEV(133, &soc_lpsc_list[21]),
 	PSC_DEV(193, &soc_lpsc_list[22]),
+	PSC_DEV(389, &soc_lpsc_list[23]),
 };
 
 const struct ti_k3_pd_platdata j784s4_pd_platdata = {
-- 
2.34.1
    • MAIN UART 5 
      • From 10161ac738d18fe2a639914a202bc6ccd50b83dd Mon Sep 17 00:00:00 2001
From: Gokul Praveen <g-praveen@ti.com>
Date: Thu, 11 Sep 2025 16:05:59 +0530
Subject: [PATCH] mainuart_5_j784s4

---
 output/j784s4/spl-hsm/clk-data.c | 3 +++
 output/j784s4/spl-hsm/dev-data.c | 1 +
 2 files changed, 4 insertions(+)

diff --git a/output/j784s4/spl-hsm/clk-data.c b/output/j784s4/spl-hsm/clk-data.c
index 6a9239c..fa3c874 100644
--- a/output/j784s4/spl-hsm/clk-data.c
+++ b/output/j784s4/spl-hsm/clk-data.c
@@ -286,6 +286,7 @@ static const struct clk_data clk_list[] = {
 	CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0),
 	CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
 	CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0),
+	CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0),
 };
 
 static const struct dev_clk soc_dev_clk_data[] = {
@@ -415,6 +416,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(398, 22, "gluelogic_hfosc0_clkout"),
 	DEV_CLK(398, 23, "board_0_hfosc1_clk_out"),
 	DEV_CLK(398, 28, "board_0_tck_out"),
+	DEV_CLK(392, 0, "usart_programmable_clock_divider_out5"),
+	DEV_CLK(392, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 };
 
 const struct ti_k3_clk_platdata j784s4_clk_platdata = {
diff --git a/output/j784s4/spl-hsm/dev-data.c b/output/j784s4/spl-hsm/dev-data.c
index f531258..94079aa 100644
--- a/output/j784s4/spl-hsm/dev-data.c
+++ b/output/j784s4/spl-hsm/dev-data.c
@@ -82,6 +82,7 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(203, &soc_lpsc_list[20]),
 	PSC_DEV(133, &soc_lpsc_list[21]),
 	PSC_DEV(193, &soc_lpsc_list[22]),
+	PSC_DEV(392, &soc_lpsc_list[17]),
 };
 
 const struct ti_k3_pd_platdata j784s4_pd_platdata = {
-- 
2.34.1