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DRA829V: Powerdown: Can RGMII6 IO stay powered?

Lennart T
Prodigy 35 points
Part Number: DRA829V

Tool/software:

Hello,

We use a DRA829V with a Marvell 88E1512 PHY. To prevent back-feeding from the PHY, we are considering keeping the RGMII6 IO supply (VDDSHV4) powered while the rest of the CPU is shut down.

Is this allowed according to the datasheet / power sequencing? Are there risks of back-currents or violating the recommended sequence? If not, what is the recommended way to prevent back-feeding from the PHY?

Thanks for your guidance!

Lennart

  • 0
    TI__Guru 52065 points

    It is NOT recommended to keep the device is a partial powered state, which is what you are describing.  The power sequencing is defined in the data manual.  The IO rails are typically first, with 3.3V IO followed by 1.8V IO.  You didn't specify which voltage you are using, so could also be a sequence violation if using 1.8V for VDDSHV4 (and other rails are 3.3V). 

    If Ethernet PHY is remaining active, the possibly the IO will also remain active?  That too could be an issue as the IO are not fail-safe, meaning they should not have voltage provided to IO when power domain (VDDSHVx) is off.

  • 0 in reply to Robert Eschler
    Prodigy 35 points

    We are planning to use 3.3 V as the IO voltage. Unfortunately, the PHY IOs cannot be electrically disabled, since the WOL signal would also be lost. Disabling only the MII is only possible via register settings.

  • +1 in reply to Lennart T
    TI__Guru 52065 points

    If MII is disabled (via register settings) prior to sleep mode, that might keep the IO connected to VDDSVH4 low.  You could use load switch (or other method) to isolate power between PHY and VDDSHV4, allowing VDDSHV4 to be disabled while PHY power remains active.  Keeping VDDSHV4 powered would not violate the power sequence, but it is a configuration that is not tested/validated - and thus not recommended.