DM8148 VPDMA

The VIP VPDMA doesn't support this kind of mirroring.

Probably we could explore the TILER mirroring feature to acheive this.

But this depends on your usecase as the VIP output for TILER should be in YUV420 and I am not sure if this is fine for your use case!!

The EDMA(not the one inside HDVPSS) can be used to do this if tiler mirroring is not capable. but extra framebuffer is required to be used by EDMA.

EDMA SW is ready in the PSP package.

Regards,

yihe

I still need your  help on:

1.  In our system, the resolution of CCD is  1920*1080, the output of each output channel is 960*1080. The pixel format is BAYER RAW, every pixel is 12bit.

Spec "sprugz8-Digital Media Processors Technical Reference Manual.pdf " describes that TILER support horizontal mirror. But there is no sufficient information for me to realize the function.

Does TI have more detailed datasheet and demo codes about TILER?

2. On suggestion to Yihe's reply about EDMA, would you help check whether the following step works?

Step1: The system allocate a full framebuffer(1920*1080*2 Byte ) and allocate a half framebuffer1(960*1080*2 Byte ).

Step2: VP0 use EDMA to move the left half image to the left half of framebuffer by one dimension to two dimensions transfer mode.  At same time, VP1 use EDMA to move the right half image to the framebuffer1 by one dimension to one dimension transfer mode.

Step3:  With the method of 2 dimension to 2 dimension, the application program open a channel of EDMA and read the pixel data from left to right in a line and line by line from framebuffer1, and then write pixel data from right to left in a line and line by line to the right area of framebuffer. When writing, the address of each pixel data(2 Bytes) in degressive way. In this way we get a complete image. We need the EDMA to adjust the size of each element.

If the above 3 steps won’t works, how to definite the function?

3. Furthermore,  if the above steps works, I would like to know whether the following step works:

Step1: VP0 connect to the output of CCD's left half image, VP1 connect to the output of CCD's right half image.

Step2: The system allocate a full framebuffer(1920*1080*2 Bytes ). The EDMA of VP0 and VP1 configured to one dimension to two dimension transfer mode.

Step3: The destination address of VP0's EDMA is the start address of framebuffer, and the storage address of every pixel(2 Bytes) in every line use increase mode.

Step4: The destination address of VP1's EDMA is the start address of framebuffer plus one line pixel's buffer length(1920*2 Bytes), and the storage address of every pixel(2 Bytes) in lines use degressive mode. The key point is that, every pixel needs two bytes, so the EDMA of VP1 need to support the storage address of every pixel (2 bytes) in a line works in degressive way, not the way ”address-1”.

If the above 4 steps works, in case of reading speeds of EDMAs of VP0 and VP1 are the same, are the writing speeds the same? Does VP's driver support in kernel? I find that DM642's EDMA supports "source address decrease" mode,  but I couldn’t find whether DM8148's EDMA  supports this mode. Would you help me on it?

Thanks

Dear yihe

  Could you answer the question that I asked on yesterday?

thanks