TMS320C6748: emif edma

Part Number: TMS320C6748

Tool/software:

When I use the emif of tms320c6748, I use two chip selectors, chip selector 2 and chip selector 4, both connected to FPGA. Chip selector 2 is used to transmit real-time data, and chip selector 4 is used to transmit non real time data. I use EDMA for reading and writing of chip selector 2, so it will not be inserted by the read and write of chip selector 4 at all. However, occasionally during the write of chip selector 2, the read and write of chip selector 4 will be inserted in the middle. I don't quite understand why during the read process of chip selector 2, chip selector 2 will not be inserted by the read and write of chip selector 4 at all. During the write process of chip selector 2, it will be inserted by the read and write of chip selector 4. I hope that the write process of chip selector 2 will not be inserted either. 

  • Hello Huan,

    We can no longer provide design support for C6748. Please refer to the notice for TI-RTOS on C6748:

     Notice regarding Processor SDK TI-RTOS for AM335x, AM437x, OMAP-L13x, C674x, K2G devices 

    https://www.ti.com/tool/download/PROCESSOR-SDK-RTOS-OMAPL138

    I have never used TI-RTOS myself (or any software on C674x). But from a "basic software concept" perspective, the only way to coordinate between 2 parts of software is to make sure that those 2 parts of software are aware of each other and able to coordinate. So if a DMA process is executing one piece of software, and a separate software task is controlling chip selector 4, and there is no way for them to interact, then there is no way to stall one read or write until the other read or write finishes.

    I am unable to provide any further guidance that is specific to C674x or your usecase. So I cannot comment on whether there are mechanisms that would allow that coordination between a DMA process and a separate software task, etc.

    Regards,

    Nick