Tool/software:
I am prototyping SW solution for TDA4AN on bargeboard with J722S and 4GB RAM. The SW is using gstreamer pipeline with tiovx plugins. As default vision firmware from SDK is prebuilt for 8GB RAM EVM, I recomile my own version using FIRMWARE-BUILDER-AM67A 11.00.00.06. There are several issues or at least documentation problems with memory maps for J722S:
psdk_rtos/docs/user_guide/developer_notes_memory_map.html, 10.7.3. Memory partitions and constraints
- RTOS <-> RTOS IPC shared region - must be 32MB size, divisible by the region size.
- vision_apps/platform/j722s/rtos/gen_linker_mem_map.py places this region at 0xA5000000, not aligned to 32M
- MPU configuration in example.syscfg files are incorrectly setting the region to 16MB size. So it compiles, but upper 16MB of IPC vring is cached. That is at least not intended.
- app_log_mem and tiovx_obj_desc_mem are together 64MB in gen_linker_mem_map.py, but only 16MB in MPU settings
- app_fileio_mem_addr and tiovx_log_rt_mem are together 32MB in gen_linker_mem_map.py, but only 16MB in MPU settings
- The documentation lacks information, that MPU and RAT setting is located in *.syscfg files, instead it wrongly states that MPU and RAT is configured in:
- /<soc>/rtos/<cpu>/<soc>_mpu_cfg.c - actually unused in J722S
- /<soc>/rtos/common/app_init.c - no appMemAddrTranslate function here
I patched the memory setting with this patch. It address the MPUs settings and also it moves carveout region to 0x8A0000000 for 4GB RAM board.
From 0655bbfcfd73583c02f26516e68b0876f07ee4cf Mon Sep 17 00:00:00 2001
From: Arnost Belohlavek <belohlavek@amit.cz>
Date: Fri, 15 Aug 2025 11:18:26 +0200
Subject: [PATCH] Move ddr_shared_mem_addr_phys to 0x8A0000000 (start at 2560MB
of RAM), fix broken MPU settings
---
vision_apps/platform/j722s/rtos/app_mem_map.h | 24 ++++-----
vision_apps/platform/j722s/rtos/c7x_1/example.syscfg | 26 ++++-----
vision_apps/platform/j722s/rtos/c7x_1/linker_mem_map.cmd | 22 ++++----
vision_apps/platform/j722s/rtos/c7x_2/example.syscfg | 26 ++++-----
vision_apps/platform/j722s/rtos/c7x_2/linker_mem_map.cmd | 22 ++++----
vision_apps/platform/j722s/rtos/gen_linker_mem_map.py | 4 +-
vision_apps/platform/j722s/rtos/gen_linker_mem_map_safertos.py | 2 +-
vision_apps/platform/j722s/rtos/k3-j722s-rtos-memory-map.dtsi | 30 +++++------
vision_apps/platform/j722s/rtos/mcu1_0/example.syscfg | 14 ++---
vision_apps/platform/j722s/rtos/mcu1_0/linker_mem_map.cmd | 10 ++--
vision_apps/platform/j722s/rtos/mcu2_0/example.syscfg | 10 ++--
vision_apps/platform/j722s/rtos/mcu2_0/example_no_board_deps.syscfg | 15 +++---
vision_apps/platform/j722s/rtos/mcu2_0/linker_mem_map.cmd | 10 ++--
vision_apps/platform/j722s/rtos/system_memory_map.html | 84 ++++++++++++++---------------
14 files changed, 149 insertions(+), 150 deletions(-)
diff --git a/vision_apps/platform/j722s/rtos/app_mem_map.h b/vision_apps/platform/j722s/rtos/app_mem_map.h
index 905fecf..29906c5 100755
--- a/vision_apps/platform/j722s/rtos/app_mem_map.h
+++ b/vision_apps/platform/j722s/rtos/app_mem_map.h
@@ -108,47 +108,47 @@
#define DDR_MCU2_0_DTS_SIZE (0x01F00000u)
/* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
-#define IPC_VRING_MEM_ADDR (0xA5000000u)
+#define IPC_VRING_MEM_ADDR (0xA6000000u)
#define IPC_VRING_MEM_SIZE (0x02000000u)
/* Memory for remote core logging [ size 256.00 KB ] */
-#define APP_LOG_MEM_ADDR (0xA7000000u)
+#define APP_LOG_MEM_ADDR (0xA8000000u)
#define APP_LOG_MEM_SIZE (0x00040000u)
/* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 63.75 MB ] */
-#define TIOVX_OBJ_DESC_MEM_ADDR (0xA7040000u)
+#define TIOVX_OBJ_DESC_MEM_ADDR (0xA8040000u)
#define TIOVX_OBJ_DESC_MEM_SIZE (0x03FC0000u)
/* Memory for remote core file operations [ size 4.00 MB ] */
-#define APP_FILEIO_MEM_ADDR (0xAB000000u)
+#define APP_FILEIO_MEM_ADDR (0xAC000000u)
#define APP_FILEIO_MEM_SIZE (0x00400000u)
/* Memory for TI OpenVX shared memory for Run-time logging. MUST be non-cached or cache-coherent [ size 28.00 MB ] */
-#define TIOVX_LOG_RT_MEM_ADDR (0xAB400000u)
+#define TIOVX_LOG_RT_MEM_ADDR (0xAC400000u)
#define TIOVX_LOG_RT_MEM_SIZE (0x01C00000u)
/* DDR for C7x_1 for Linux IPC [ size 1024.00 KB ] */
-#define DDR_C7x_1_IPC_ADDR (0xAD000000u)
+#define DDR_C7x_1_IPC_ADDR (0xAE000000u)
#define DDR_C7x_1_IPC_SIZE (0x00100000u)
/* DDR for C7x_1 for all sections, used for reserving memory in DTS file [ size 63.00 MB ] */
-#define DDR_C7x_1_DTS_ADDR (0xAD100000u)
+#define DDR_C7x_1_DTS_ADDR (0xAE100000u)
#define DDR_C7x_1_DTS_SIZE (0x03F00000u)
/* DDR for C7x_2 for Linux IPC [ size 1024.00 KB ] */
-#define DDR_C7x_2_IPC_ADDR (0xB1000000u)
+#define DDR_C7x_2_IPC_ADDR (0xB2000000u)
#define DDR_C7x_2_IPC_SIZE (0x00100000u)
/* DDR for C7x_2 for all sections, used for reserving memory in DTS file [ size 63.00 MB ] */
-#define DDR_C7x_2_DTS_ADDR (0xB1100000u)
+#define DDR_C7x_2_DTS_ADDR (0xB2100000u)
#define DDR_C7x_2_DTS_SIZE (0x03F00000u)
/* DDR for MCU1_0 for local heap [ size 8.00 MB ] */
-#define DDR_MCU1_0_LOCAL_HEAP_ADDR (0xB5000000u)
+#define DDR_MCU1_0_LOCAL_HEAP_ADDR (0xB6000000u)
#define DDR_MCU1_0_LOCAL_HEAP_SIZE (0x00800000u)
/* DDR for MCU2_0 for local heap [ size 32.00 MB ] */
-#define DDR_MCU2_0_LOCAL_HEAP_ADDR (0xB5800000u)
+#define DDR_MCU2_0_LOCAL_HEAP_ADDR (0xB6800000u)
#define DDR_MCU2_0_LOCAL_HEAP_SIZE (0x02000000u)
/* Memory for shared memory buffers in DDR [ size 512.00 MB ] */
@@ -252,7 +252,7 @@
#define DDR_C7X_2_SCRATCH_PHYS_SIZE (0x04000000u)
/* memory for shared memory buffers in high DDR [ size 512.00 MB ] */
-#define DDR_SHARED_MEM_PHYS_ADDR (0x900000000u)
+#define DDR_SHARED_MEM_PHYS_ADDR (0x8A0000000u)
#define DDR_SHARED_MEM_PHYS_SIZE (0x20000000u)
#define DDR_64BIT_BASE_VADDR (0x100000000u)
diff --git a/vision_apps/platform/j722s/rtos/c7x_1/example.syscfg b/vision_apps/platform/j722s/rtos/c7x_1/example.syscfg
index be38053..c27eb96 100644
--- a/vision_apps/platform/j722s/rtos/c7x_1/example.syscfg
+++ b/vision_apps/platform/j722s/rtos/c7x_1/example.syscfg
@@ -148,14 +148,14 @@ mmu_armv88.attribute = "MAIR0";
/**
* DDR_C7x_1_DTS
- * Region start: 0xAD200000
- * Region end: 0xAD200000
+ * Region start: 0xAE200000
+ * Region end: 0xAE200000
* Read and write for both privileged and user modes.
* Attribute is MAIR7.
*/
mmu_armv89.$name = "DDR_C7x_1_DTS";
-mmu_armv89.vAddr = 0xAD200000;
-mmu_armv89.pAddr = 0xAD200000;
+mmu_armv89.vAddr = 0xAE200000;
+mmu_armv89.pAddr = 0xAE200000;
mmu_armv89.size = 0x3E00000;
mmu_armv89.attribute = "MAIR7";
@@ -168,33 +168,33 @@ mmu_armv89.attribute = "MAIR7";
*/
mmu_armv810.$name = "DDR_SHARED_MEM";
mmu_armv810.vAddr = 0xC0000000;
-mmu_armv810.pAddr = 0x900000000;
+mmu_armv810.pAddr = 0x8A0000000;
mmu_armv810.size = 0x20000000;
mmu_armv810.attribute = "MAIR7";
/**
* DDR_SHARED_MEM_NON_CACHE
- * Region start: 0xA5000000
- * Region end: 0xA500000
+ * Region start: 0xA6000000
+ * Region end: 0xA600000
* Read and write for both privileged and user modes.
* Attribute is MAIR4.
*/
mmu_armv811.$name = "DDR_SHARED_MEM_NON_CACHE";
-mmu_armv811.vAddr = 0xA5000000;
-mmu_armv811.pAddr = 0xA5000000;
+mmu_armv811.vAddr = 0xA6000000;
+mmu_armv811.pAddr = 0xA6000000;
mmu_armv811.size = 0x8000000;
mmu_armv811.attribute = "MAIR4";
/**
* DDR_C7X_1_IPC
- * Region start: 0xAD000000
- * Region end: 0xAD000000
+ * Region start: 0xAE000000
+ * Region end: 0xAE000000
* Read and write for both privileged and user modes.
* Attribute is MAIR4.
*/
mmu_armv812.$name = "DDR_C7X_1_IPC";
-mmu_armv812.vAddr = 0xAD000000;
-mmu_armv812.pAddr = 0xAD000000;
+mmu_armv812.vAddr = 0xAE000000;
+mmu_armv812.pAddr = 0xAE000000;
mmu_armv812.size = 0x200000;
mmu_armv812.attribute = "MAIR4";
diff --git a/vision_apps/platform/j722s/rtos/c7x_1/linker_mem_map.cmd b/vision_apps/platform/j722s/rtos/c7x_1/linker_mem_map.cmd
index 2e476eb..b26eaa4 100644
--- a/vision_apps/platform/j722s/rtos/c7x_1/linker_mem_map.cmd
+++ b/vision_apps/platform/j722s/rtos/c7x_1/linker_mem_map.cmd
@@ -73,27 +73,27 @@ MEMORY
/* L1 for C7x_1 [ size 16.00 KB ] */
L2RAM_C7x_1_AUX_AS_L1 ( RWIX ) : ORIGIN = 0x7F03C000 , LENGTH = 0x00004000
/* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
- IPC_VRING_MEM : ORIGIN = 0xA5000000 , LENGTH = 0x02000000
+ IPC_VRING_MEM : ORIGIN = 0xA6000000 , LENGTH = 0x02000000
/* Memory for remote core logging [ size 256.00 KB ] */
- APP_LOG_MEM : ORIGIN = 0xA7000000 , LENGTH = 0x00040000
+ APP_LOG_MEM : ORIGIN = 0xA8000000 , LENGTH = 0x00040000
/* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 63.75 MB ] */
- TIOVX_OBJ_DESC_MEM : ORIGIN = 0xA7040000 , LENGTH = 0x03FC0000
+ TIOVX_OBJ_DESC_MEM : ORIGIN = 0xA8040000 , LENGTH = 0x03FC0000
/* Memory for remote core file operations [ size 4.00 MB ] */
- APP_FILEIO_MEM : ORIGIN = 0xAB000000 , LENGTH = 0x00400000
+ APP_FILEIO_MEM : ORIGIN = 0xAC000000 , LENGTH = 0x00400000
/* DDR for C7x_1 for Linux IPC [ size 1024.00 KB ] */
- DDR_C7x_1_IPC ( RWIX ) : ORIGIN = 0xAD000000 , LENGTH = 0x00100000
+ DDR_C7x_1_IPC ( RWIX ) : ORIGIN = 0xAE000000 , LENGTH = 0x00100000
/* DDR for C7x_1 for Linux resource table [ size 1024 B ] */
- DDR_C7x_1_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xAD100000 , LENGTH = 0x00000400
+ DDR_C7x_1_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xAE100000 , LENGTH = 0x00000400
/* DDR for C7x_1 for Linux IPC trace [ size 1023.00 KB ] */
- DDR_C7x_1_IPC_TRACE ( RWIX ) : ORIGIN = 0xAD100400 , LENGTH = 0x000FFC00
+ DDR_C7x_1_IPC_TRACE ( RWIX ) : ORIGIN = 0xAE100400 , LENGTH = 0x000FFC00
/* DDR for C7x_1 for boot section [ size 1024 B ] */
- DDR_C7x_1_BOOT ( RWIX ) : ORIGIN = 0xAD200000 , LENGTH = 0x00000400
+ DDR_C7x_1_BOOT ( RWIX ) : ORIGIN = 0xAE200000 , LENGTH = 0x00000400
/* DDR for C7x_1 for vecs section [ size 16.00 KB ] */
- DDR_C7x_1_VECS ( RWIX ) : ORIGIN = 0xAD400000 , LENGTH = 0x00004000
+ DDR_C7x_1_VECS ( RWIX ) : ORIGIN = 0xAE400000 , LENGTH = 0x00004000
/* DDR for C7x_1 for secure vecs section [ size 16.00 KB ] */
- DDR_C7x_1_SECURE_VECS ( RWIX ) : ORIGIN = 0xAD600000 , LENGTH = 0x00004000
+ DDR_C7x_1_SECURE_VECS ( RWIX ) : ORIGIN = 0xAE600000 , LENGTH = 0x00004000
/* DDR for C7x_1 for code/data [ size 57.98 MB ] */
- DDR_C7x_1 ( RWIX ) : ORIGIN = 0xAD604000 , LENGTH = 0x039FC000
+ DDR_C7x_1 ( RWIX ) : ORIGIN = 0xAE604000 , LENGTH = 0x039FC000
/* Memory for shared memory buffers in DDR [ size 512.00 MB ] */
DDR_SHARED_MEM : ORIGIN = 0xC0000000 , LENGTH = 0x20000000
/* DDR for c7x_1 for non cacheable local heap [ size 64.00 MB ] */
diff --git a/vision_apps/platform/j722s/rtos/c7x_2/example.syscfg b/vision_apps/platform/j722s/rtos/c7x_2/example.syscfg
index 349243c..da3dcd4 100644
--- a/vision_apps/platform/j722s/rtos/c7x_2/example.syscfg
+++ b/vision_apps/platform/j722s/rtos/c7x_2/example.syscfg
@@ -148,14 +148,14 @@ mmu_armv88.attribute = "MAIR0";
/**
* DDR_C7x_2_DTS
- * Region start: 0xB1200000
- * Region end: 0xB1200000
+ * Region start: 0xB2200000
+ * Region end: 0xB2200000
* Read and write for both privileged and user modes.
* Attribute is MAIR7.
*/
mmu_armv89.$name = "DDR_C7x_2_DTS";
-mmu_armv89.vAddr = 0xB1200000;
-mmu_armv89.pAddr = 0xB1200000;
+mmu_armv89.vAddr = 0xB2200000;
+mmu_armv89.pAddr = 0xB2200000;
mmu_armv89.size = 0x3E00000;
mmu_armv89.attribute = "MAIR7";
@@ -168,33 +168,33 @@ mmu_armv89.attribute = "MAIR7";
*/
mmu_armv810.$name = "DDR_SHARED_MEM";
mmu_armv810.vAddr = 0xC0000000;
-mmu_armv810.pAddr = 0x900000000;
+mmu_armv810.pAddr = 0x8A0000000;
mmu_armv810.size = 0x20000000;
mmu_armv810.attribute = "MAIR7";
/**
* DDR_C7X_2_SHARED_MEM_NON_CACHE
- * Region start: 0xA5000000
- * Region end: 0xA500000
+ * Region start: 0xA6000000
+ * Region end: 0xA600000
* Read and write for both privileged and user modes.
* Attribute is MAIR4.
*/
mmu_armv811.$name = "DDR_C7X_2_SHARED_MEM_NON_CACHE";
-mmu_armv811.vAddr = 0xA5000000;
-mmu_armv811.pAddr = 0xA5000000;
+mmu_armv811.vAddr = 0xA6000000;
+mmu_armv811.pAddr = 0xA6000000;
mmu_armv811.size = 0x8000000;
mmu_armv811.attribute = "MAIR4";
/**
* DDR_C7X_2_IPC
- * Region start: 0xB1000000
- * Region end: 0xB1000000
+ * Region start: 0xB2000000
+ * Region end: 0xB2000000
* Read and write for both privileged and user modes.
* Attribute is MAIR4.
*/
mmu_armv812.$name = "DDR_C7X_2_IPC";
-mmu_armv812.vAddr = 0xB1000000;
-mmu_armv812.pAddr = 0xB1000000;
+mmu_armv812.vAddr = 0xB2000000;
+mmu_armv812.pAddr = 0xB2000000;
mmu_armv812.size = 0x200000;
mmu_armv812.attribute = "MAIR4";
diff --git a/vision_apps/platform/j722s/rtos/c7x_2/linker_mem_map.cmd b/vision_apps/platform/j722s/rtos/c7x_2/linker_mem_map.cmd
index 18e647e..2246621 100644
--- a/vision_apps/platform/j722s/rtos/c7x_2/linker_mem_map.cmd
+++ b/vision_apps/platform/j722s/rtos/c7x_2/linker_mem_map.cmd
@@ -73,27 +73,27 @@ MEMORY
/* L1 for C7x_2 [ size 16.00 KB ] */
L2RAM_C7x_2_AUX_AS_L1 ( RWIX ) : ORIGIN = 0x7F83C000 , LENGTH = 0x00004000
/* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
- IPC_VRING_MEM : ORIGIN = 0xA5000000 , LENGTH = 0x02000000
+ IPC_VRING_MEM : ORIGIN = 0xA6000000 , LENGTH = 0x02000000
/* Memory for remote core logging [ size 256.00 KB ] */
- APP_LOG_MEM : ORIGIN = 0xA7000000 , LENGTH = 0x00040000
+ APP_LOG_MEM : ORIGIN = 0xA8000000 , LENGTH = 0x00040000
/* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 63.75 MB ] */
- TIOVX_OBJ_DESC_MEM : ORIGIN = 0xA7040000 , LENGTH = 0x03FC0000
+ TIOVX_OBJ_DESC_MEM : ORIGIN = 0xA8040000 , LENGTH = 0x03FC0000
/* Memory for remote core file operations [ size 4.00 MB ] */
- APP_FILEIO_MEM : ORIGIN = 0xAB000000 , LENGTH = 0x00400000
+ APP_FILEIO_MEM : ORIGIN = 0xAC000000 , LENGTH = 0x00400000
/* DDR for C7x_2 for Linux IPC [ size 1024.00 KB ] */
- DDR_C7x_2_IPC ( RWIX ) : ORIGIN = 0xB1000000 , LENGTH = 0x00100000
+ DDR_C7x_2_IPC ( RWIX ) : ORIGIN = 0xB2000000 , LENGTH = 0x00100000
/* DDR for C7x_2 for Linux resource table [ size 1024 B ] */
- DDR_C7x_2_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xB1100000 , LENGTH = 0x00000400
+ DDR_C7x_2_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xB2100000 , LENGTH = 0x00000400
/* DDR for C7x_2 for Linux IPC trace [ size 1023.00 KB ] */
- DDR_C7x_2_IPC_TRACE ( RWIX ) : ORIGIN = 0xB1100400 , LENGTH = 0x000FFC00
+ DDR_C7x_2_IPC_TRACE ( RWIX ) : ORIGIN = 0xB2100400 , LENGTH = 0x000FFC00
/* DDR for C7x_2 for boot section [ size 1024 B ] */
- DDR_C7x_2_BOOT ( RWIX ) : ORIGIN = 0xB1200000 , LENGTH = 0x00000400
+ DDR_C7x_2_BOOT ( RWIX ) : ORIGIN = 0xB2200000 , LENGTH = 0x00000400
/* DDR for C7x_2 for vecs section [ size 16.00 KB ] */
- DDR_C7x_2_VECS ( RWIX ) : ORIGIN = 0xB1400000 , LENGTH = 0x00004000
+ DDR_C7x_2_VECS ( RWIX ) : ORIGIN = 0xB2400000 , LENGTH = 0x00004000
/* DDR for C7x_2 for secure vecs section [ size 16.00 KB ] */
- DDR_C7x_2_SECURE_VECS ( RWIX ) : ORIGIN = 0xB1600000 , LENGTH = 0x00004000
+ DDR_C7x_2_SECURE_VECS ( RWIX ) : ORIGIN = 0xB2600000 , LENGTH = 0x00004000
/* DDR for C7x_2 for code/data [ size 57.98 MB ] */
- DDR_C7x_2 ( RWIX ) : ORIGIN = 0xB1604000 , LENGTH = 0x039FC000
+ DDR_C7x_2 ( RWIX ) : ORIGIN = 0xB2604000 , LENGTH = 0x039FC000
/* Memory for shared memory buffers in DDR [ size 512.00 MB ] */
DDR_SHARED_MEM : ORIGIN = 0xC0000000 , LENGTH = 0x20000000
/* Virtual address of non-cacheable DDR for c7x_1 for local heap wrt c7x_2 [ size 64.00 MB ] */
diff --git a/vision_apps/platform/j722s/rtos/gen_linker_mem_map.py b/vision_apps/platform/j722s/rtos/gen_linker_mem_map.py
index 18a008d..d361362 100755
--- a/vision_apps/platform/j722s/rtos/gen_linker_mem_map.py
+++ b/vision_apps/platform/j722s/rtos/gen_linker_mem_map.py
@@ -171,7 +171,7 @@ mcu2_0_ddr_size = 32*MB - (mcu2_0_ddr_addr-mcu2_0_ddr_ipc_addr);
#
# Hardcoding this value, as this cannot be different from IPC echo test value
-ipc_vring_mem_addr = 0xA5000000;
+ipc_vring_mem_addr = 0xA6000000;
ipc_vring_mem_size = 32*MB;
app_log_mem_addr = ipc_vring_mem_addr + ipc_vring_mem_size;
@@ -272,7 +272,7 @@ c7x_2_1_ddr_local_heap_addr = c7x_1_ddr_local_heap_addr;
c7x_2_1_ddr_scratch_addr = c7x_1_ddr_scratch_addr;
# Shared memory for DMA Buf FD carveout (located in high mem)
-ddr_shared_mem_addr_phys = 0x900000000;
+ddr_shared_mem_addr_phys = 0x8A0000000;
#
# Create memory section based on addr and size defined above, including
diff --git a/vision_apps/platform/j722s/rtos/gen_linker_mem_map_safertos.py b/vision_apps/platform/j722s/rtos/gen_linker_mem_map_safertos.py
index 2f5c1c5..5449cf5 100755
--- a/vision_apps/platform/j722s/rtos/gen_linker_mem_map_safertos.py
+++ b/vision_apps/platform/j722s/rtos/gen_linker_mem_map_safertos.py
@@ -245,7 +245,7 @@ c7x_2_ddr_scratch_size = 112*MB;
c7x_core_heap_hi_size += c7x_2_ddr_scratch_size
# Shared memory for DMA Buf FD carveout (located in high mem)
-ddr_shared_mem_addr_phys = 0x900000000; # TODO: Clean this up
+ddr_shared_mem_addr_phys = 0x8A0000000; # TODO: Clean this up
ddr_shared_mem_size = 512*MB;
#
diff --git a/vision_apps/platform/j722s/rtos/k3-j722s-rtos-memory-map.dtsi b/vision_apps/platform/j722s/rtos/k3-j722s-rtos-memory-map.dtsi
index a9af97f..66cc2dd 100644
--- a/vision_apps/platform/j722s/rtos/k3-j722s-rtos-memory-map.dtsi
+++ b/vision_apps/platform/j722s/rtos/k3-j722s-rtos-memory-map.dtsi
@@ -36,39 +36,39 @@
reg = <0x00 0xa2100000 0x00 0x01f00000>;
no-map;
};
- vision_apps_rtos_ipc_memory_region: vision-apps-rtos-ipc-memory-region@a5000000 {
+ vision_apps_rtos_ipc_memory_region: vision-apps-rtos-ipc-memory-region@a6000000 {
compatible = "shared-dma-pool";
- reg = <0x00 0xa5000000 0x00 0x02000000>;
+ reg = <0x00 0xa6000000 0x00 0x02000000>;
no-map;
};
- vision_apps_memory_region: vision-apps-dma-memory@a7000000 {
+ vision_apps_memory_region: vision-apps-dma-memory@a8000000 {
compatible = "shared-dma-pool";
- reg = <0x00 0xa7000000 0x00 0x06000000>;
+ reg = <0x00 0xa8000000 0x00 0x06000000>;
no-map;
};
- vision_apps_c71_0_dma_memory_region: vision-apps-c71-dma-memory@ad000000 {
+ vision_apps_c71_0_dma_memory_region: vision-apps-c71-dma-memory@ae000000 {
compatible = "shared-dma-pool";
- reg = <0x00 0xad000000 0x00 0x00100000>;
+ reg = <0x00 0xae000000 0x00 0x00100000>;
no-map;
};
- vision_apps_c71_0_memory_region: vision-apps-c71_0-memory@ad100000 {
+ vision_apps_c71_0_memory_region: vision-apps-c71_0-memory@ae100000 {
compatible = "shared-dma-pool";
- reg = <0x00 0xad100000 0x00 0x03f00000>;
+ reg = <0x00 0xae100000 0x00 0x03f00000>;
no-map;
};
- vision_apps_c71_1_dma_memory_region: vision-apps-c71_1-dma-memory@b1000000 {
+ vision_apps_c71_1_dma_memory_region: vision-apps-c71_1-dma-memory@b2000000 {
compatible = "shared-dma-pool";
- reg = <0x00 0xb1000000 0x00 0x00100000>;
+ reg = <0x00 0xb2000000 0x00 0x00100000>;
no-map;
};
- vision_apps_c71_1_memory_region: vision-apps-c71_1-memory@b1100000 {
+ vision_apps_c71_1_memory_region: vision-apps-c71_1-memory@b2100000 {
compatible = "shared-dma-pool";
- reg = <0x00 0xb1100000 0x00 0x03f00000>;
+ reg = <0x00 0xb2100000 0x00 0x03f00000>;
no-map;
};
- vision_apps_core_heaps_lo: vision-apps-core-heap-memory-lo@b5000000 {
+ vision_apps_core_heaps_lo: vision-apps-core-heap-memory-lo@b6000000 {
compatible = "shared-dma-pool";
- reg = <0x00 0xb5000000 0x00 0x02800000>;
+ reg = <0x00 0xb6000000 0x00 0x02800000>;
no-map;
};
c7x_ddr_heaps_hi: c7x-ddr-heaps-hi@880000000 {
@@ -78,6 +78,6 @@
};
vision_apps_shared_region: vision_apps_shared-memories {
compatible = "dma-heap-carveout";
- reg = <0x09 0x00000000 0x00 0x20000000>;
+ reg = <0x08 0xa0000000 0x00 0x20000000>;
};
diff --git a/vision_apps/platform/j722s/rtos/mcu1_0/example.syscfg b/vision_apps/platform/j722s/rtos/mcu1_0/example.syscfg
index 7802af1..6a8fbb7 100644
--- a/vision_apps/platform/j722s/rtos/mcu1_0/example.syscfg
+++ b/vision_apps/platform/j722s/rtos/mcu1_0/example.syscfg
@@ -81,20 +81,20 @@ mpu_armv78.allowExecute = false;
mpu_armv78.$name = "RESOURCE_TABLE_AND_TRACE";
mpu_armv78.attributes = "NonCached";
-mpu_armv79.baseAddr = 0xA5000000;
-mpu_armv79.size = 24; /* 32 MB */
+mpu_armv79.baseAddr = 0xA6000000;
+mpu_armv79.size = 25; /* 32 MB */
mpu_armv79.allowExecute = false;
mpu_armv79.$name = "RTOS_IPC_VRING";
mpu_armv79.attributes = "NonCached";
-mpu_armv710.baseAddr = 0xA7000000;
-mpu_armv710.size = 24;
+mpu_armv710.baseAddr = 0xA8000000;
+mpu_armv710.size = 26;
mpu_armv710.allowExecute = false;
mpu_armv710.$name = "TIOVX_RUN_TIME_LOGGING1";
mpu_armv710.attributes = "NonCached";
-mpu_armv711.baseAddr = 0xAB000000;
-mpu_armv711.size = 24;
+mpu_armv711.baseAddr = 0xAC000000;
+mpu_armv711.size = 25;
mpu_armv711.allowExecute = false;
mpu_armv711.$name = "TIOVX_RUN_TIME_LOGGING2";
mpu_armv711.attributes = "NonCached";
@@ -110,4 +110,4 @@ debug_log.uartLog.WKUP_UART.TXD.$suggestSolution = "WKUP_UART0_TXD";
addr_translate1.$name = "CONFIG_ADDR_TRANSLATE_REGION0";
addr_translate1.localAddr = 0xC0000000;
-addr_translate1.systemAddr = 0x900000000;
+addr_translate1.systemAddr = 0x8A0000000;
diff --git a/vision_apps/platform/j722s/rtos/mcu1_0/linker_mem_map.cmd b/vision_apps/platform/j722s/rtos/mcu1_0/linker_mem_map.cmd
index d913435..3dcd672 100755
--- a/vision_apps/platform/j722s/rtos/mcu1_0/linker_mem_map.cmd
+++ b/vision_apps/platform/j722s/rtos/mcu1_0/linker_mem_map.cmd
@@ -83,15 +83,15 @@ MEMORY
/* DDR for MCU1_0 for code/data [ size 14.00 MB ] */
DDR_MCU1_0 ( RWIX ) : ORIGIN = 0xA0200000 , LENGTH = 0x00E00000
/* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
- IPC_VRING_MEM : ORIGIN = 0xA5000000 , LENGTH = 0x02000000
+ IPC_VRING_MEM : ORIGIN = 0xA6000000 , LENGTH = 0x02000000
/* Memory for remote core logging [ size 256.00 KB ] */
- APP_LOG_MEM : ORIGIN = 0xA7000000 , LENGTH = 0x00040000
+ APP_LOG_MEM : ORIGIN = 0xA8000000 , LENGTH = 0x00040000
/* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 63.75 MB ] */
- TIOVX_OBJ_DESC_MEM : ORIGIN = 0xA7040000 , LENGTH = 0x03FC0000
+ TIOVX_OBJ_DESC_MEM : ORIGIN = 0xA8040000 , LENGTH = 0x03FC0000
/* Memory for remote core file operations [ size 4.00 MB ] */
- APP_FILEIO_MEM : ORIGIN = 0xAB000000 , LENGTH = 0x00400000
+ APP_FILEIO_MEM : ORIGIN = 0xAC000000 , LENGTH = 0x00400000
/* DDR for MCU1_0 for local heap [ size 8.00 MB ] */
- DDR_MCU1_0_LOCAL_HEAP ( RWIX ) : ORIGIN = 0xB5000000 , LENGTH = 0x00800000
+ DDR_MCU1_0_LOCAL_HEAP ( RWIX ) : ORIGIN = 0xB6000000 , LENGTH = 0x00800000
/* Memory for shared memory buffers in DDR [ size 512.00 MB ] */
DDR_SHARED_MEM : ORIGIN = 0xC0000000 , LENGTH = 0x20000000
}
diff --git a/vision_apps/platform/j722s/rtos/mcu2_0/example.syscfg b/vision_apps/platform/j722s/rtos/mcu2_0/example.syscfg
index d25457e..ee15462 100644
--- a/vision_apps/platform/j722s/rtos/mcu2_0/example.syscfg
+++ b/vision_apps/platform/j722s/rtos/mcu2_0/example.syscfg
@@ -110,19 +110,19 @@ mpu_armv78.$name = "RESOURCE_TABLE_AND_TRACE";
mpu_armv78.attributes = "NonCached";
mpu_armv79.baseAddr = 0xA5000000;
-mpu_armv79.size = 24; /* 32 MB */
+mpu_armv79.size = 25; /* 32 MB */
mpu_armv79.allowExecute = false;
mpu_armv79.$name = "RTOS_IPC_VRING";
mpu_armv79.attributes = "NonCached";
mpu_armv710.baseAddr = 0xA7000000;
-mpu_armv710.size = 24;
+mpu_armv710.size = 26;
mpu_armv710.allowExecute = false;
mpu_armv710.$name = "TIOVX_RUN_TIME_LOGGING1";
mpu_armv710.attributes = "NonCached";
-mpu_armv711.baseAddr = 0xAB000000;
-mpu_armv711.size = 24;
+mpu_armv711.baseAddr = 0xAC000000;
+mpu_armv711.size = 25;
mpu_armv711.allowExecute = false;
mpu_armv711.$name = "TIOVX_RUN_TIME_LOGGING2";
mpu_armv711.attributes = "NonCached";
@@ -170,4 +170,4 @@ i2c2.I2C.SDA.$suggestSolution = "GPMC0_CSn3";
addr_translate1.$name = "CONFIG_ADDR_TRANSLATE_REGION0";
addr_translate1.localAddr = 0xC0000000;
-addr_translate1.systemAddr = 0x900000000;
+addr_translate1.systemAddr = 0x8A0000000;
diff --git a/vision_apps/platform/j722s/rtos/mcu2_0/example_no_board_deps.syscfg b/vision_apps/platform/j722s/rtos/mcu2_0/example_no_board_deps.syscfg
index ac75253..4668a40 100644
--- a/vision_apps/platform/j722s/rtos/mcu2_0/example_no_board_deps.syscfg
+++ b/vision_apps/platform/j722s/rtos/mcu2_0/example_no_board_deps.syscfg
@@ -78,25 +78,24 @@ mpu_armv78.allowExecute = false;
mpu_armv78.$name = "RESOURCE_TABLE_AND_TRACE";
mpu_armv78.attributes = "NonCached";
-mpu_armv79.baseAddr = 0xA5000000;
-mpu_armv79.size = 24; /* 32 MB */
+mpu_armv79.baseAddr = 0xA6000000;
+mpu_armv79.size = 25; /* 32 MB */
mpu_armv79.allowExecute = false;
mpu_armv79.$name = "RTOS_IPC_VRING";
mpu_armv79.attributes = "NonCached";
-mpu_armv710.baseAddr = 0xA7000000;
-mpu_armv710.size = 24;
+mpu_armv710.baseAddr = 0xA8000000;
+mpu_armv710.size = 26;
mpu_armv710.allowExecute = false;
mpu_armv710.$name = "TIOVX_RUN_TIME_LOGGING1";
mpu_armv710.attributes = "NonCached";
-mpu_armv711.baseAddr = 0xAB000000;
-mpu_armv711.size = 24;
+mpu_armv711.baseAddr = 0xAC000000;
+mpu_armv711.size = 25;
mpu_armv711.allowExecute = false;
mpu_armv711.$name = "TIOVX_RUN_TIME_LOGGING2";
mpu_armv711.attributes = "NonCached";
-
addr_translate1.$name = "CONFIG_ADDR_TRANSLATE_REGION0";
addr_translate1.localAddr = 0xC0000000;
-addr_translate1.systemAddr = 0x900000000;
+addr_translate1.systemAddr = 0x8A0000000;
diff --git a/vision_apps/platform/j722s/rtos/mcu2_0/linker_mem_map.cmd b/vision_apps/platform/j722s/rtos/mcu2_0/linker_mem_map.cmd
index 954a4b4..ffbb277 100644
--- a/vision_apps/platform/j722s/rtos/mcu2_0/linker_mem_map.cmd
+++ b/vision_apps/platform/j722s/rtos/mcu2_0/linker_mem_map.cmd
@@ -81,15 +81,15 @@ MEMORY
/* DDR for MCU2_0 for code/data [ size 30.00 MB ] */
DDR_MCU2_0 ( RWIX ) : ORIGIN = 0xA2200000 , LENGTH = 0x01E00000
/* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
- IPC_VRING_MEM : ORIGIN = 0xA5000000 , LENGTH = 0x02000000
+ IPC_VRING_MEM : ORIGIN = 0xA6000000 , LENGTH = 0x02000000
/* Memory for remote core logging [ size 256.00 KB ] */
- APP_LOG_MEM : ORIGIN = 0xA7000000 , LENGTH = 0x00040000
+ APP_LOG_MEM : ORIGIN = 0xA8000000 , LENGTH = 0x00040000
/* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 63.75 MB ] */
- TIOVX_OBJ_DESC_MEM : ORIGIN = 0xA7040000 , LENGTH = 0x03FC0000
+ TIOVX_OBJ_DESC_MEM : ORIGIN = 0xA8040000 , LENGTH = 0x03FC0000
/* Memory for remote core file operations [ size 4.00 MB ] */
- APP_FILEIO_MEM : ORIGIN = 0xAB000000 , LENGTH = 0x00400000
+ APP_FILEIO_MEM : ORIGIN = 0xAC000000 , LENGTH = 0x00400000
/* DDR for MCU2_0 for local heap [ size 32.00 MB ] */
- DDR_MCU2_0_LOCAL_HEAP ( RWIX ) : ORIGIN = 0xB5800000 , LENGTH = 0x02000000
+ DDR_MCU2_0_LOCAL_HEAP ( RWIX ) : ORIGIN = 0xB6800000 , LENGTH = 0x02000000
/* Memory for shared memory buffers in DDR [ size 512.00 MB ] */
DDR_SHARED_MEM : ORIGIN = 0xC0000000 , LENGTH = 0x20000000
}
diff --git a/vision_apps/platform/j722s/rtos/system_memory_map.html b/vision_apps/platform/j722s/rtos/system_memory_map.html
index 9bf6c12..10a5e21 100644
--- a/vision_apps/platform/j722s/rtos/system_memory_map.html
+++ b/vision_apps/platform/j722s/rtos/system_memory_map.html
@@ -138,168 +138,168 @@
</tr>
<tr>
<td class="tg-kftd">IPC_VRING_MEM</td>
- <td class="tg-kftd">0xA5000000</td>
- <td class="tg-kftd">0xA6FFFFFF</td>
+ <td class="tg-kftd">0xA6000000</td>
+ <td class="tg-kftd">0xA7FFFFFF</td>
<td class="tg-kftd">32.00 MB</td>
<td class="tg-kftd"></td>
<td class="tg-kftd">Memory for IPC Vring's. MUST be non-cached or cache-coherent</td>
</tr>
<tr>
<td class="tg-6sgx">APP_LOG_MEM</td>
- <td class="tg-6sgx">0xA7000000</td>
- <td class="tg-6sgx">0xA703FFFF</td>
+ <td class="tg-6sgx">0xA8000000</td>
+ <td class="tg-6sgx">0xA803FFFF</td>
<td class="tg-6sgx">256.00 KB</td>
<td class="tg-6sgx"></td>
<td class="tg-6sgx">Memory for remote core logging</td>
</tr>
<tr>
<td class="tg-kftd">TIOVX_OBJ_DESC_MEM</td>
- <td class="tg-kftd">0xA7040000</td>
- <td class="tg-kftd">0xAAFFFFFF</td>
+ <td class="tg-kftd">0xA8040000</td>
+ <td class="tg-kftd">0xABFFFFFF</td>
<td class="tg-kftd">63.75 MB</td>
<td class="tg-kftd"></td>
<td class="tg-kftd">Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent</td>
</tr>
<tr>
<td class="tg-6sgx">APP_FILEIO_MEM</td>
- <td class="tg-6sgx">0xAB000000</td>
- <td class="tg-6sgx">0xAB3FFFFF</td>
+ <td class="tg-6sgx">0xAC000000</td>
+ <td class="tg-6sgx">0xAC3FFFFF</td>
<td class="tg-6sgx"> 4.00 MB</td>
<td class="tg-6sgx"></td>
<td class="tg-6sgx">Memory for remote core file operations</td>
</tr>
<tr>
<td class="tg-kftd">TIOVX_LOG_RT_MEM</td>
- <td class="tg-kftd">0xAB400000</td>
- <td class="tg-kftd">0xACFFFFFF</td>
+ <td class="tg-kftd">0xAC400000</td>
+ <td class="tg-kftd">0xADFFFFFF</td>
<td class="tg-kftd">28.00 MB</td>
<td class="tg-kftd"></td>
<td class="tg-kftd">Memory for TI OpenVX shared memory for Run-time logging. MUST be non-cached or cache-coherent</td>
</tr>
<tr>
<td class="tg-6sgx">DDR_C7x_1_IPC</td>
- <td class="tg-6sgx">0xAD000000</td>
- <td class="tg-6sgx">0xAD0FFFFF</td>
+ <td class="tg-6sgx">0xAE000000</td>
+ <td class="tg-6sgx">0xAE0FFFFF</td>
<td class="tg-6sgx">1024.00 KB</td>
<td class="tg-6sgx">RWIX</td>
<td class="tg-6sgx">DDR for C7x_1 for Linux IPC</td>
</tr>
<tr>
<td class="tg-kftd">DDR_C7x_1_RESOURCE_TABLE</td>
- <td class="tg-kftd">0xAD100000</td>
- <td class="tg-kftd">0xAD1003FF</td>
+ <td class="tg-kftd">0xAE100000</td>
+ <td class="tg-kftd">0xAE1003FF</td>
<td class="tg-kftd">1024 B</td>
<td class="tg-kftd">RWIX</td>
<td class="tg-kftd">DDR for C7x_1 for Linux resource table</td>
</tr>
<tr>
<td class="tg-6sgx">DDR_C7x_1_IPC_TRACE</td>
- <td class="tg-6sgx">0xAD100400</td>
- <td class="tg-6sgx">0xAD1FFFFF</td>
+ <td class="tg-6sgx">0xAE100400</td>
+ <td class="tg-6sgx">0xAE1FFFFF</td>
<td class="tg-6sgx">1023.00 KB</td>
<td class="tg-6sgx">RWIX</td>
<td class="tg-6sgx">DDR for C7x_1 for Linux IPC trace</td>
</tr>
<tr>
<td class="tg-kftd">DDR_C7x_1_BOOT</td>
- <td class="tg-kftd">0xAD200000</td>
- <td class="tg-kftd">0xAD2003FF</td>
+ <td class="tg-kftd">0xAE200000</td>
+ <td class="tg-kftd">0xAE2003FF</td>
<td class="tg-kftd">1024 B</td>
<td class="tg-kftd">RWIX</td>
<td class="tg-kftd">DDR for C7x_1 for boot section</td>
</tr>
<tr>
<td class="tg-6sgx">DDR_C7x_1_VECS</td>
- <td class="tg-6sgx">0xAD400000</td>
- <td class="tg-6sgx">0xAD403FFF</td>
+ <td class="tg-6sgx">0xAE400000</td>
+ <td class="tg-6sgx">0xAE403FFF</td>
<td class="tg-6sgx">16.00 KB</td>
<td class="tg-6sgx">RWIX</td>
<td class="tg-6sgx">DDR for C7x_1 for vecs section</td>
</tr>
<tr>
<td class="tg-kftd">DDR_C7x_1_SECURE_VECS</td>
- <td class="tg-kftd">0xAD600000</td>
- <td class="tg-kftd">0xAD603FFF</td>
+ <td class="tg-kftd">0xAE600000</td>
+ <td class="tg-kftd">0xAE603FFF</td>
<td class="tg-kftd">16.00 KB</td>
<td class="tg-kftd">RWIX</td>
<td class="tg-kftd">DDR for C7x_1 for secure vecs section</td>
</tr>
<tr>
<td class="tg-6sgx">DDR_C7x_1</td>
- <td class="tg-6sgx">0xAD604000</td>
- <td class="tg-6sgx">0xB0FFFFFF</td>
+ <td class="tg-6sgx">0xAE604000</td>
+ <td class="tg-6sgx">0xB1FFFFFF</td>
<td class="tg-6sgx">57.98 MB</td>
<td class="tg-6sgx">RWIX</td>
<td class="tg-6sgx">DDR for C7x_1 for code/data</td>
</tr>
<tr>
<td class="tg-kftd">DDR_C7x_2_IPC</td>
- <td class="tg-kftd">0xB1000000</td>
- <td class="tg-kftd">0xB10FFFFF</td>
+ <td class="tg-kftd">0xB2000000</td>
+ <td class="tg-kftd">0xB20FFFFF</td>
<td class="tg-kftd">1024.00 KB</td>
<td class="tg-kftd">RWIX</td>
<td class="tg-kftd">DDR for C7x_2 for Linux IPC</td>
</tr>
<tr>
<td class="tg-6sgx">DDR_C7x_2_RESOURCE_TABLE</td>
- <td class="tg-6sgx">0xB1100000</td>
- <td class="tg-6sgx">0xB11003FF</td>
+ <td class="tg-6sgx">0xB2100000</td>
+ <td class="tg-6sgx">0xB21003FF</td>
<td class="tg-6sgx">1024 B</td>
<td class="tg-6sgx">RWIX</td>
<td class="tg-6sgx">DDR for C7x_2 for Linux resource table</td>
</tr>
<tr>
<td class="tg-kftd">DDR_C7x_2_IPC_TRACE</td>
- <td class="tg-kftd">0xB1100400</td>
- <td class="tg-kftd">0xB11FFFFF</td>
+ <td class="tg-kftd">0xB2100400</td>
+ <td class="tg-kftd">0xB21FFFFF</td>
<td class="tg-kftd">1023.00 KB</td>
<td class="tg-kftd">RWIX</td>
<td class="tg-kftd">DDR for C7x_2 for Linux IPC trace</td>
</tr>
<tr>
<td class="tg-6sgx">DDR_C7x_2_BOOT</td>
- <td class="tg-6sgx">0xB1200000</td>
- <td class="tg-6sgx">0xB12003FF</td>
+ <td class="tg-6sgx">0xB2200000</td>
+ <td class="tg-6sgx">0xB22003FF</td>
<td class="tg-6sgx">1024 B</td>
<td class="tg-6sgx">RWIX</td>
<td class="tg-6sgx">DDR for C7x_2 for boot section</td>
</tr>
<tr>
<td class="tg-kftd">DDR_C7x_2_VECS</td>
- <td class="tg-kftd">0xB1400000</td>
- <td class="tg-kftd">0xB1403FFF</td>
+ <td class="tg-kftd">0xB2400000</td>
+ <td class="tg-kftd">0xB2403FFF</td>
<td class="tg-kftd">16.00 KB</td>
<td class="tg-kftd">RWIX</td>
<td class="tg-kftd">DDR for C7x_2 for vecs section</td>
</tr>
<tr>
<td class="tg-6sgx">DDR_C7x_2_SECURE_VECS</td>
- <td class="tg-6sgx">0xB1600000</td>
- <td class="tg-6sgx">0xB1603FFF</td>
+ <td class="tg-6sgx">0xB2600000</td>
+ <td class="tg-6sgx">0xB2603FFF</td>
<td class="tg-6sgx">16.00 KB</td>
<td class="tg-6sgx">RWIX</td>
<td class="tg-6sgx">DDR for C7x_2 for secure vecs section</td>
</tr>
<tr>
<td class="tg-kftd">DDR_C7x_2</td>
- <td class="tg-kftd">0xB1604000</td>
- <td class="tg-kftd">0xB4FFFFFF</td>
+ <td class="tg-kftd">0xB2604000</td>
+ <td class="tg-kftd">0xB5FFFFFF</td>
<td class="tg-kftd">57.98 MB</td>
<td class="tg-kftd">RWIX</td>
<td class="tg-kftd">DDR for C7x_2 for code/data</td>
</tr>
<tr>
<td class="tg-6sgx">DDR_MCU1_0_LOCAL_HEAP</td>
- <td class="tg-6sgx">0xB5000000</td>
- <td class="tg-6sgx">0xB57FFFFF</td>
+ <td class="tg-6sgx">0xB6000000</td>
+ <td class="tg-6sgx">0xB67FFFFF</td>
<td class="tg-6sgx"> 8.00 MB</td>
<td class="tg-6sgx">RWIX</td>
<td class="tg-6sgx">DDR for MCU1_0 for local heap</td>
</tr>
<tr>
<td class="tg-kftd">DDR_MCU2_0_LOCAL_HEAP</td>
- <td class="tg-kftd">0xB5800000</td>
- <td class="tg-kftd">0xB77FFFFF</td>
+ <td class="tg-kftd">0xB6800000</td>
+ <td class="tg-kftd">0xB87FFFFF</td>
<td class="tg-kftd">32.00 MB</td>
<td class="tg-kftd">RWIX</td>
<td class="tg-kftd">DDR for MCU2_0 for local heap</td>
--
2.39.5
I rebuild firmware for all cores (MPU1_0 included) and I rebuild user space libraries. Now I am running gustom distribution based on Debian. The kernel is form LINUX-SDK, gstreamer that includes all meta-edgeai patches and tiovx gstremaer plugins.
Now I am able to pass all conformance tests and run gstremaer pipelines from EVM. Using 4 cameras via V3link:
gst-launch-1.0 \
v4l2src device=/dev/video-imx219-cam0 io-mode=5 ! video/x-bayer,width=1920,height=1080,framerate=30/1,format=bggr ! queue leaky=2 ! \
tiovxisp sink_0::device=/dev/v4l-imx219-subdev0 sensor-name=SENSOR_SONY_IMX219_RPI dcc-isp-file=/opt/imaging/imx219/linear/dcc_viss_1920x1080.bin \
sink_0::dcc-2a-file=/opt/imaging/imx219/linear/dcc_2a_1920x1080.bin format-msb=7 sink_0::pool-size=8 src::pool-size=8 ! \
video/x-raw,format=NV12, width=1920,height=1080 ! tiovxmultiscaler ! video/x-raw, format=NV12, width=640, height=480 ! queue ! mosaic.sink_0 \
v4l2src device=/dev/video-imx219-cam1 io-mode=5 ! video/x-bayer,width=1920,height=1080,framerate=30/1,format=bggr ! queue leaky=2 ! \
tiovxisp sink_0::device=/dev/v4l-imx219-subdev1 sensor-name=SENSOR_SONY_IMX219_RPI dcc-isp-file=/opt/imaging/imx219/linear/dcc_viss_1920x1080.bin \
sink_0::dcc-2a-file=/opt/imaging/imx219/linear/dcc_2a_1920x1080.bin format-msb=7 sink_0::pool-size=8 src::pool-size=8 ! \
video/x-raw,format=NV12, width=1920,height=1080 ! tiovxmultiscaler ! video/x-raw, format=NV12, width=640, height=480 ! queue ! mosaic.sink_1 \
v4l2src device=/dev/video-imx219-cam2 io-mode=5 ! video/x-bayer,width=1920,height=1080,framerate=30/1,format=bggr ! queue leaky=2 ! \
tiovxisp sink_0::device=/dev/v4l-imx219-subdev2 sensor-name=SENSOR_SONY_IMX219_RPI dcc-isp-file=/opt/imaging/imx219/linear/dcc_viss_1920x1080.bin \
sink_0::dcc-2a-file=/opt/imaging/imx219/linear/dcc_2a_1920x1080.bin format-msb=7 sink_0::pool-size=8 src::pool-size=8 ! \
video/x-raw,format=NV12, width=1920,height=1080 ! tiovxmultiscaler ! video/x-raw, format=NV12, width=640, height=480 ! queue ! mosaic.sink_2 \
v4l2src device=/dev/video-imx219-cam3 io-mode=5 ! video/x-bayer,width=1920,height=1080,framerate=30/1,format=bggr ! queue leaky=2 ! \
tiovxisp sink_0::device=/dev/v4l-imx219-subdev3 sensor-name=SENSOR_SONY_IMX219_RPI dcc-isp-file=/opt/imaging/imx219/linear/dcc_viss_1920x1080.bin \
sink_0::dcc-2a-file=/opt/imaging/imx219/linear/dcc_2a_1920x1080.bin format-msb=7 sink_0::pool-size=8 src::pool-size=8 ! \
video/x-raw,format=NV12, width=1920,height=1080 ! tiovxmultiscaler ! video/x-raw, format=NV12, width=640, height=480 ! queue ! mosaic.sink_3 \
tiovxmosaic name=mosaic \
sink_0::startx="<0>" sink_0::starty="<0>" sink_0::widths="<640>" sink_0::heights="<480>" \
sink_1::startx="<0>" sink_1::starty="<480>" sink_1::widths="<640>" sink_1::heights="<480>" \
sink_2::startx="<640>" sink_2::starty="<0>" sink_2::widths="<640>" sink_2::heights="<480>" \
sink_3::startx="<640>" sink_3::starty="<480>" sink_3::widths="<640>" sink_3::heights="<480>" ! \
video/x-raw, width=1920, height=1080 ! kmssink driver-name=tidss sync=false force-modesetting=true
But there all still two issues.
- Sometimes firmware hangs during startup, the logs show the boot of the cores, but boot never finish. I will add the log as soon as I reproduce it again.
- The gstreamer pipeline above usually hangs on first start after device power up. Second start of the pipeline runs smoothly. I'm not sure, that it is really SW issue, it may be problem with my test setup.
I would like to ask for validation of memory setup and also for update of the documentation. The inconsistencies between linker, MPU and documentation is at least confusing and probably really buggy.
And I would like to ask for somu gude or hints how to debug vision apps boot to collect more detailed information.
