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TDA4VEN-Q1: Layout questions about LPDDR4 in EVM

Xingyu Zhu
Expert 4335 points
Part Number: TDA4VEN-Q1


Tool/software:

Hi expert,

Our customer is doing the layout for TDA4VEN. Here are some questions about LPDDR4 layout in EVM:

1. The calculated impedance is 103ohm and the target impedance is 133ohm, it also exceeds the impedance control in below table. Could you please help check the difference?

2. The target width and separation is 3.2 and 16. While in the actual board, the separation is 0.11mm and the width is 0.17mm. Could you please check this difference? Thanks

Best Regards,

Xingyu Zhu

  • 0
    TI__Guru 53825 points

    #1:  It is understood the target impedance of the T-branch segments may not be achievable on most PCB stack-up.  The goal should be to get as close as 2x the base/trunk trace impedance as possible.  One strategy that can help is to low the base/trunk trace impedance.  For example - lowing from 40-ohms to 33-ohms can low the T-branch segment from 80ohms (2x base) to 66-ohms.  If the best SE impedance achievable is 56-ohms (just an example) - that is much closer to 66-ohm comparted to 80-ohms. Similar strategy can be used with differential traces.  

    #2:  I'm assuming this will create an impedance discontinuity and simulations will need to be performed to determine impact.