AM623: Conception clarification for (LP)DDR4 training Algorithm

Tool/software:

Hi, Dear Expert

To create this thread for double checking and concept clarification.

This is extension discussion thread from one years ago.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1406455/am623-are-there-any-special-test-conditions-for-the-shmoo-test-on-the-am6234?tisearch=e2e-sitesearch&keymatch=shmoo%20am62

Ref. this information for (LP)DDR4 training algorithm, it tell us what's the DDR training function done.

https://dev.ti.com/tirex/content/Processor_DDR_Config_0.10.32.0000/docs/README.html

Few question,

(1) As far as I know, both DDR4 or LPDDR4 need training? (Y/N)

(2) (LP)DDR4 Training is done by AM62 itself? (Y/N)

(3) Base on current status, SHMOO tool only support LPDDR4 only? (Y/N)

(4) We saw some training items, some function label "LPDDR4 only", does it mean DDR4 does not need this training item? (Y/N)

• IO calibration of the controller/PHY (DDR4 and LPDDR4)
• Command Bus Training (CBT), including reference voltage programmed in MR12 of DRAM (LPDDR4 only)
• CA/CS leveling (LPDDR4 only)
• Write leveling (DDR4 and LPDDR4)
• Read Gate Training (DDR4 and LPDDR4)
• Read Leveling (Read Data Eye Training) (DDR4 and LPDDR4)
• VREF Training (DDR4 and LPDDR4)
• Write DQ Leveling (Write Data Eye Training) (LPDDR4 only)

(5) I saw an keyword "normal operation" in README, what's the definition for "normal operation"? (Y/N)

Thank You Very Much

Gibbs