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TDA4VH-Q1: LPDDR4_Layout query

manoj j
Prodigy 30 points

Part Number: TDA4VH-Q1

Tool/software:

Hi Team,

In our project, we are using XTDA4VH. According to the Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) document, the differential impedance for the T-branch is 70/140 Ω trace impedance. Our board stackup lacks the 70 Ω trace impedance. Can we utilize the 50 Ω trace impedance for single ended and 100 Ω trace impedance for differential line instead?

  • 0
    TI__Guru 54915 points

    The goal is to maintain a constant impedance along the entire length of the connection.  When a trace is split in two segments, the impedance seen at the source is half.  Thus to maintain the same impedance between the trace (trunk) and the 2 segments (T-branch) - the impedance is doubled.  That is why a trunk trace of 35-ohms is routed as 70-ohms for the T-branch segments.

    If you are going to route a trace at 50-ohms single ended - then the T-branch segment will need to be 100-ohms (single ended). That is likely not achievable in your PCB.  In fact, the recommended 70ohms may not be achievable.  However - the 70-ohms will be much closer to the achievable impedance compared with 100-ohms.  That is why we recommended lower impedances (35-ohms vs 50-ohms).

  • 0 in reply to Robert Eschler
    Prodigy 30 points

    1. If I am maintaining a 50 ohms trace impedance what could be impact on LPDDR memory side. 

    2. If I am not maintaining a 70 ohms trace impedance what could be impact on LPDDR memory side.

  • 0 in reply to manoj j
    TI__Guru 54915 points

    Different trace impedances require different termination settings for the memory.  How closely those match will impact signal integrity and performance.  The recommendation is to simulate the interface with your implemented traces and selected termination values to see how system performs.  This is discussed in previously referenced LPDDR4 design application note.