Tool/software:
TDA4APE custom board
SDK 11.0
freertos+linux
The theoretical DDR bandwidth of our board is 4266M * 32 * 2 / 8 = 34GB/s.
We found that when all the cameras were functioning properly, the average bandwidth obtained through appPerfStatsDdrStatsPrint was 12GB/S.
When we attempted to further increase the DDR bandwidth by using the stressapptest program, the DDR bandwidth obtained by appPerfStatsDdrStatsPrint did not show any significant increase. Moreover, after a few minutes, the board seemed to undergo a reset.
1.We would like to know if 12GB/s has reached the bandwidth bottleneck. If so, why is it much lower than the theoretical bandwidth? Is this reasonable?
2.We attempted to increase the bandwidth solely by running the stressapptest program, but we found that even when the CPU was fully utilized, it could only increase to 8GB/S, failing to reach 12GB/S. If we want to test the bandwidth limit independently, does TI have any relevant testing procedures and documentation?