AM6442: Cortex-R5F I2C GPMC transmission timing on AM6442

Hello ,

What is the PSRAM size and bits of operation?

Can you please confirm did you interface the PSRAM or FPGA ?

If you interface with PSRAM memory, please share the datasheet.

Please confirm if the timing in between two writes for 11 clock cycles is not meeting the actual throughput ?

Are you OK going with DMA if you want to improve the throughput?

Regards,

Anil.

Hello,

Sorry, we are using FPGA here and do not use wait signal. The following is the relevant configuration information of GMPC in syscfg.

Chip Select On Time                       1

Chip Select Read Off Time             10

Chip Select Write Off Time             10

ADV On Time                                   2

ADV Read Off Time                          5

ADV Write Off Time                           5

ADV AADMux On Time                     2

ADV AADMux Read Off Time            5

ADV AADMux Write Off Time            5

WE On Time                                      6

WE Off Time                                      9

OE On Time                                      6

OE Off Time                                      9

OE AADMux On Time                       6

OE AADMux Off Time                       9

Page Burst Access Delay                 0

Read Access Time                            8

Write Access Time                            9

Read Cycle Time                              11

Write Cycle Time                              11

Write Data AAD Mux Bus Time         5

Bus Turn Around Time                      0

Cycle to Cycle Delay                         2

Cycle Delay Same Chip Select        Add...

Cycle Delay Different Chip Select    Add...

Hello ,

The above timing information is OK.

Please provide the answers for all the above queries as well.

Regards,

Anil.

Hello,

We use FPGA to mimic NOR FLASH timing. We use 256MB of space and a 32 bit bus, and we do not use WAIT signal and DIR signal. The time interval between two write operations should be reduced to two clock cycles to meet the required throughput.

Hello ,

You cannot force back-to-back single asynchronous write transactions to be only 2 GPMC cycles .
The controller must wait until the device’s minimum write cycle completes, so your observed ~11 cycles (driver/ADV/address overhead + device min cycle) cannot be compressed to 2 cycles.

Why 2 cycles is impossible in your setup :
• PSRAM datasheet gives tWC / tACC ≈ 70 ns. At f_GPMC = 100 MHz a cycle = 10 ns → tWC = 7 cycles.

The controller cannot start the next write until the current write cycle timing requirement is met.
• AD-multiplexing (address phase) and small extra CS/WE hold times can add cycles, so seeing 11 cycles is expected. 

Practical ways to improve overall throughput :
Use DMA :
• Throughput gains are large because the per-transaction device timing (tWC) is still required, but you remove CPU inter-write delays and reduce AD/address overhead by doing long contiguous block writes.

Regards,

Anil.

Hello,

I apologize for my incorrect expression. The following image is the timing diagram captured during two writes, Now we want to adjust the 11 clock cycles marked between the red lines in the picture.