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TDA4VM-Q1: Booting Linux via MMCSD w/SBL

Gibbs Shih
Expert 6500 points

Part Number: TDA4VM-Q1

Tool/software:

Dear Expert,

I am try to test MMCSD Linux boot w/ SBL only.

Ref as below.

https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/10_00_00_05/exports/docs/pdk_jacinto_10_00_00_27/docs/userguide/jacinto/boot/boot_app.html

I have an bootable SD, it include boot partition and rootfs partition.

Boot partition file list as below.

<pre><font color="#4E9A06"><b>gibbs@gibbs-HP-ZBook-15-G5</b></font>:<font color="#3465A4"><b>~/work/j721e/tftpboot/sbl_test_boot</b></font>$ ll /media/gibbs/boot/
total 21230
drwxr-xr-x  2 gibbs gibbs     1536  一   1  1970 <font color="#3465A4"><b>.</b></font>/
drwxr-x---+ 4 root  root      4096  九  18 20:15 <font color="#3465A4"><b>..</b></font>/
-rw-r--r--  1 gibbs gibbs   535660  九  18 20:04 atf_optee.appimage
-rw-r--r--  1 gibbs gibbs     2552  九  18 20:06 lateapp1
-rw-r--r--  1 gibbs gibbs   222036  九  18 20:07 lateapp2
-rw-r--r--  1 gibbs gibbs     1680  九  18 20:07 lateapp3
-rw-r--r--  1 gibbs gibbs   307695  九  18 20:12 tiboot3.bin
-rw-r--r--  1 gibbs gibbs   113456  九  18 20:04 tidtb_linux.appimage
-rw-r--r--  1 gibbs gibbs   263114  九  18 20:03 tifs.bin
-rw-r--r--  1 gibbs gibbs 20286024  九  18 20:05 tikernelimage_linux.appimage
</pre>

lateapp1 = multicore_MCU2_0_MCU2_1_stage1.appimage

lateapp2 = multicore_DSPs_MCU3_0_MCU3_1_stage2.appimage

lateapp3 = multicore_MPU1_0_stage3.appimage

But I found boot failed.

MCU Uart log as below.

Do I miss anything?

Need your suggestion.

SDK : ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27

Device type : GP (I already check I use GP type image)

01000000011a00006a3765730000000000000000475020200101010001010100

ibbs@gibbs-HP-ZBook-15-G5:~/work/j721e$ python3 7080.uart_boot_socid.py device_type_evm.txt 
-----------------------
SoC ID Header Info:
-----------------------
NumBlocks            : [1]
-----------------------
SoC ID Public ROM Info:
-----------------------
SubBlockId           :
SubBlockSize         :
DeviceName           : j7es
DeviceType           : GP  
DMSC ROM Version     : [0, 1, 1, 1]
R5 ROM Version       : [0, 1, 1, 1]

Thank You Very Much

Gibbs

  • 0
    TI__Mastermind 19080 points

    Hi Gibbs,

    I guess you have missed the 4th and 5th step in the process(ie: building and copying the bootapp step).

    Regards

    Gokul

  • 0 in reply to Gokul Praveen
    TI__Expert 6500 points

    Hi, Gokul

    I make a mistake, you are right. 

    It can work for me now.

    Another concept clarification,

    Bacically, lateapp1/2/3 can be my "custoerized application image" for each different Core

    Step as below.

    To stitch multiple .rprc images into a multicore image, execute the following command

    For Linux:
<PDK>/packages/ti/boot/sbl/tools/multicoreImageGen/bin/MulticoreImageGen LE 55 output.appimage  <core_id_1> core_1.rprc <core_id_2> core_2.rprc

    Is it correct ?

    Thank You Very Much.

    Gibbs

  • 0 in reply to Gibbs Shih
    TI__Mastermind 19080 points

    Hi GIbbs,

    Sorry for the delay. I have redirected this query to the corresponding PDK expert. Thanks in advance for your patience.

    Regards

    Gokul

  • 0 in reply to Gokul Praveen
    TI__Genius 16550 points

    Hi Gibbs,

    Could you please refer to the following steps, let us know if that helps.

    Working Directory (Path):
    karthikeyansaravanan@LAP678U:~/ti/ti-processor-sdk-rtos-j721e-evm-11_00_00_06/pdk_jacinto_11_00_00_21/packages/ti/binary/GPIO_Baremetal_LedBlink_TestApp/bin/j721e_evm$

    Command to stitch multiple .rprc images into a single multicore image:
    /home/karthikeyansaravanan/ti/ti-processor-sdk-rtos-j721e-evm-11_00_00_06/pdk_jacinto_11_00_00_21/packages/ti/boot/sbl/tools/multicoreImageGen/bin/MulticoreImageGen LE 55 Multicore_app 11 GPIO_Baremetal_LedBlink_TestApp_mcu2_1_release.rprc 10 GPIO_Baremetal_LedBlink_TestApp_mcu2_0_release.rprc

    Output File Name:
    Multicore_app

    Regards,

    Karthik

  • 0 in reply to Karthikeyan S
    TI__Expert 6500 points

    Hello Karthik,

    Sorry late reply.

    I follow your instruction to build multicore image successfully, which called "Multicore_app"

    Here are my copy image in SD Boot paretition.

    cp -f ./sbl_mmcsd_img_mcu1_0_release.tiimage /media/gibbs/boot/tiboot3.bin
cp -f ./tifs.bin /media/gibbs/boot
cp -f ./sbl_boot_app_mmcsd_j721e_evm_mcu1_0_freertos_TestApp_release.appimage /media/gibbs/boot/app
cp -f ./Multicore_app /media/gibbs/boot/lateapp1
cp -f ./multicore_images/j721e_evm/multicore_DSPs_MCU3_0_MCU3_1_stage2.appimage /media/gibbs/boot/lateapp2
cp -f ./multicore_images/j721e_evm/multicore_MPU1_0_stage3.appimage /media/gibbs/boot/lateapp3

    After boot from SD, it seems boot failed, log as below.

    it seems hang on execute "lateapp1"

    Welcome to minicom 2.7.1

OPTIONS: I18n 
Compiled on Dec 23 2019, 02:06:26.
Port /dev/ttyUSB1, 15:04:47

Press CTRL-A Z for help on special keys

SBL Revision: 01.00.10.01 (Sep 18 2025 - 13:18:27)
TIFS  ver: 10.0.8--v10.00.08 (Fiery Fox)
Starting Sciserver..... PASSED
MCU R5F App started at 2250 usecs
Loading BootImage

 BootApp_MMCBootImageLate: fp 0x 0x41c12300, fileName is 0:/lateapp1

    Normal boot should be like below.

    SBL Revision: 01.00.10.01 (Sep 18 2025 - 13:18:27)
TIFS  ver: 10.0.8--v10.00.08 (Fiery Fox)
Starting Sciserver..... PASSED
MCU R5F App started at 2251 usecs
Loading BootImage

 BootApp_MMCBootImageLate: fp 0x 0x41c12300, fileName is 0:/lateapp1

 Called SBL_MulticoreImageParse, status = 0
BootImage completed, status = 0
SBL_SlaveCoreBoot completed for Core ID#10, Entry point is 0x70014000
SBL_SlaveCoreBoot completed for Core ID#11, Entry point is 0x70016000
Loading BootImage

 BootApp_MMCBootImageLate: fp 0x 0x41c12300, fileName is 0:/lateapp2

 Called SBL_MulticoreImageParse, status = 0
BootImage completed, status = 0
SBL_SlaveCoreBoot completed for Core ID#12, Entry point is 0x70018000
SBL_SlaveCoreBoot completed for Core ID#13, Entry point is 0x7001a000
SBL_SlaveCoreBoot completed for Core ID#16, Entry point C66X_0 booted
is 0x90030000
SBL_SlaveCoreBoot completed for Core ID#17, Entry point is 0x90930000C66X_1 booted

SBL_SlaveCoreBoot completed for Core ID#18, Entry poC7X_0 booted
int is 0x91a00000
Loading BootImage

 BootApp_MMCBootImageLate: fp 0x 0x41c12300, fileName is 0:/lateapp3

 Called SBL_MulticoreImageParse, status = 0
BootImage completed, status = 0
SBL_SlaveCoreBoot completed for Core ID#0, Entry point is 0x70024000
MPU1_0 booted
Boot App: Started at 2471 usec
Boot App: Total Num booted cores = 8
Boot App: Booted Core ID #10 at 37477 usecs
Boot App: Booted Core ID #11 at 38105 usecs
Boot App: Booted Core ID #12 at 143610 usecs
Boot App: Booted Core ID #13 at 144237 usecs
Boot App: Booted Core ID #16 at 145077 usecs
Boot App: Booted Core ID #17 at 145914 usecs
Boot App: Booted Core ID #18 at 146558 usecs
Boot App: Booted Core ID #0 at 154146 usecs
MCU Boot Task started at 2471 usecs and finished at 168581 usecs
MCU2_0 booted
MCU2_1 booted
MCU3_0 booted
MCU3_1 booted
lateapps booted successfully
MCU2_0 reports: All tests have passed

    I think "LedBlink_TestApp_mcu2_0" or "I think "LedBlink_TestApp_mcu2_1" should be work failed, because I do not see any flash LED on EVB

    Do I miss any thing?

    Can any multicore image which we combained for booting? Any limition?

    Thank You.

    Gibbs

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/sbl_5F00_mmcsd_5F00_img_5F00_mcu1_5F00_0_5F00_release.tiimage

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0207.tifs.bin

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/sbl_5F00_boot_5F00_app_5F00_mmcsd_5F00_j721e_5F00_evm_5F00_mcu1_5F00_0_5F00_freertos_5F00_TestApp_5F00_release.appimage

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/Multicore_5F00_app

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/8540.multicore_5F00_DSPs_5F00_MCU3_5F00_0_5F00_MCU3_5F00_1_5F00_stage2.appimage

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/2364.multicore_5F00_MPU1_5F00_0_5F00_stage3.appimage

  • 0 in reply to Gibbs Shih
    TI__Genius 16550 points

    Hi Gibbs,

    Could you please double-check the _resetvectors address in both example binaries? They should not be the same, as having identical addresses can lead to improper execution.

    Regards,

    Karthik

  • 0 in reply to Karthikeyan S
    TI__Expert 6500 points

    Hi, Karthik

    Few question from my side.

    (1) Could you tell me How to check "_resetvectors" address in "binaries" ? 

    if we want to combine these two app images.

    * GPIO_Baremetal_LedBlink_TestApp_mcu2_0_release.rprc

    * GPIO_Baremetal_LedBlink_TestApp_mcu2_1_release.rprc

    MulticoreImageGen LE 55 Multicore_app 11 GPIO_Baremetal_LedBlink_TestApp_mcu2_1_release.rprc 10 GPIO_Baremetal_LedBlink_TestApp_mcu2_0_release.rprc

    Here are some information what I know about "_resetvectors" from *.map w/ MCU 2_0 & 2_1 (GPIO_Baremetal_LedBlink_TestApp_mcu2_x_release.rprc)

    ******************************************************************************
            TI ARM Clang Linker Unix v3.2.2                    
******************************************************************************
>> Linked Tue Oct  7 13:48:57 2025

OUTPUT FILE NAME:   </home/gibbs/work/j721e/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/binary/GPIO_Baremetal_LedBlink_TestApp/bin/j721e_evm/GPIO_Baremetal_LedBlink_TestApp_mcu2_0_release.xer5f>
ENTRY POINT SYMBOL: "_resetvectors"  address: 41ce3000


MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
  MCU0_R5F_TCMA_SBL_RSV 00000000   00000100  00000000  00000100     X
  MCU0_R5F_TCMA         00000100   00007f00  00000000  00007f00     X
  MCU0_R5F_TCMB0        41010000   00008000  00000000  00008000  RWIX
  MCU0_R5F1_ATCM        41400000   00008000  00000000  00008000  RWIX
  MCU0_R5F1_BTCM        41410000   00008000  00000000  00008000  RWIX
  OCMC_RAM_BOARD_CFG    41c80000   00002000  00000000  00002000  RWIX
  OCMC_RAM_SCISERVER    41c82000   00060000  00000000  00060000  RWIX
  VECTORS               41ce2000   00001000  00000000  00001000     X
  RESET_VECTORS         41ce3000   00000100  00000040  000000c0     X
  OCMC_RAM              41ce3100   0001ca00  00000000  0001ca00  RWIX
  OCMC_RAM_X509_HEADER  41cffb00   00000500  00000000  00000500  RWIX
  MSMC3_ARM_FW          70000000   00020000  00000000  00020000  RWIX
  MSMC3                 70020000   007d0000  000007a0  007cf860  RWIX
  MSMC3_DMSC_FW         707f0000   00010000  00000000  00010000  RWIX
  DDR0                  80000000   80000000  00026b28  7ffd94d8  RWIX


SEGMENT ALLOCATION MAP

run origin  load origin   length   init length attrs members
----------  ----------- ---------- ----------- ----- -------
41ce3000    41ce3000    00000040   00000040    r-x
  41ce3000    41ce3000    00000040   00000040    r-x .rstvectors
70020000    70020000    000007a0   000007a0    r-x
  70020000    70020000    00000370   00000370    r-x .startupCode
  70020370    70020370    00000318   00000318    r-- .startupData
  70020688    70020688    00000118   00000118    r-x .bootCode
80000000    80000000    0000c900   00000000    rw-
  80000000    80000000    0000c900   00000000    rw- .data
8000c900    8000c900    0000f8e0   0000f8e0    r-x
  8000c900    8000c900    0000af20   0000af20    r-x .text
  80017820    80017820    000049c0   000049c0    r-- .rodata
8001c1e0    8001c1e0    000013a0   00000000    rw-
  8001c1e0    8001c1e0    000013a0   00000000    rw- .bss
8001d580    8001d580    000025a8   000025a8    r--
  8001d580    8001d580    000025a8   000025a8    r-- .cinit
ffff9000    ffff9000    00005000   00000000    r--
  ffff9000    ffff9000    00001000   00000000    r-- .undStack
  ffffa000    ffffa000    00001000   00000000    r-- .svcStack
  ffffb000    ffffb000    00001000   00000000    r-- .irqStack
  ffffc000    ffffc000    00001000   00000000    r-- .fiqStack
  ffffd000    ffffd000    00001000   00000000    r-- .abortStack
ffffe000    ffffe000    00002000   00000000    rw-
  ffffe000    ffffe000    00002000   00000000    rw- .stack


    ******************************************************************************
            TI ARM Clang Linker Unix v3.2.2                    
******************************************************************************
>> Linked Tue Oct  7 13:53:27 2025

OUTPUT FILE NAME:   </home/gibbs/work/j721e/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/binary/GPIO_Baremetal_LedBlink_TestApp/bin/j721e_evm/GPIO_Baremetal_LedBlink_TestApp_mcu2_1_release.xer5f>
ENTRY POINT SYMBOL: "_resetvectors"  address: 41ce3000


MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
  MCU0_R5F_TCMA_SBL_RSV 00000000   00000100  00000000  00000100     X
  MCU0_R5F_TCMA         00000100   00007f00  00000000  00007f00     X
  MCU0_R5F_TCMB0        41010000   00008000  00000000  00008000  RWIX
  MCU0_R5F1_ATCM        41400000   00008000  00000000  00008000  RWIX
  MCU0_R5F1_BTCM        41410000   00008000  00000000  00008000  RWIX
  OCMC_RAM_BOARD_CFG    41c80000   00002000  00000000  00002000  RWIX
  OCMC_RAM_SCISERVER    41c82000   00060000  00000000  00060000  RWIX
  VECTORS               41ce2000   00001000  00000000  00001000     X
  RESET_VECTORS         41ce3000   00000100  00000040  000000c0     X
  OCMC_RAM              41ce3100   0001ca00  00000000  0001ca00  RWIX
  OCMC_RAM_X509_HEADER  41cffb00   00000500  00000000  00000500  RWIX
  MSMC3_ARM_FW          70000000   00020000  00000000  00020000  RWIX
  MSMC3                 70020000   007d0000  000007a0  007cf860  RWIX
  MSMC3_DMSC_FW         707f0000   00010000  00000000  00010000  RWIX
  DDR0                  80000000   80000000  00026b28  7ffd94d8  RWIX


SEGMENT ALLOCATION MAP

run origin  load origin   length   init length attrs members
----------  ----------- ---------- ----------- ----- -------
41ce3000    41ce3000    00000040   00000040    r-x
  41ce3000    41ce3000    00000040   00000040    r-x .rstvectors
70020000    70020000    000007a0   000007a0    r-x
  70020000    70020000    00000370   00000370    r-x .startupCode
  70020370    70020370    00000318   00000318    r-- .startupData
  70020688    70020688    00000118   00000118    r-x .bootCode
80000000    80000000    0000c900   00000000    rw-
  80000000    80000000    0000c900   00000000    rw- .data
8000c900    8000c900    0000f8e0   0000f8e0    r-x
  8000c900    8000c900    0000af20   0000af20    r-x .text
  80017820    80017820    000049c0   000049c0    r-- .rodata
8001c1e0    8001c1e0    000013a0   00000000    rw-
  8001c1e0    8001c1e0    000013a0   00000000    rw- .bss
8001d580    8001d580    000025a8   000025a8    r--
  8001d580    8001d580    000025a8   000025a8    r-- .cinit
ffff9000    ffff9000    00005000   00000000    r--
  ffff9000    ffff9000    00001000   00000000    r-- .undStack
  ffffa000    ffffa000    00001000   00000000    r-- .svcStack
  ffffb000    ffffb000    00001000   00000000    r-- .irqStack
  ffffc000    ffffc000    00001000   00000000    r-- .fiqStack
  ffffd000    ffffd000    00001000   00000000    r-- .abortStack
ffffe000    ffffe000    00002000   00000000    rw-
  ffffe000    ffffe000    00002000   00000000    rw- .stack

     

    Orginal demo app w/ MCU 2_0 & 2_1 should be like below, (app_boot_test_j721e_evm_mcu2_xTestApp_release)

    ******************************************************************************
            TI ARM Clang Linker Unix v3.2.2                    
******************************************************************************
>> Linked Thu Sep 18 13:32:35 2025

OUTPUT FILE NAME:   </home/gibbs/work/j721e/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/boot/sbl/example/k3MulticoreApp/binary/j721e/bootapp_boot_test_j721e_evm_mcu2_0TestApp_release.xer5f>
ENTRY POINT SYMBOL: "_sblTestResetVectors"  address: 70014000


MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
  MSMC3_MCU1_CPU0       70010000   00002000  00000000  00002000  RWIX
  MSMC3_MCU1_CPU1       70012000   00002000  00000000  00002000  RWIX
  MSMC3_MCU2_CPU0       70014000   00002000  00000538  00001ac8  RWIX
  MSMC3_MCU2_CPU1       70016000   00002000  00000000  00002000  RWIX
  MSMC3_MCU3_CPU0       70018000   00002000  00000000  00002000  RWIX
  MSMC3_MCU3_CPU1       7001a000   00002000  00000000  00002000  RWIX
  MSMC3_DSP1_C66X       7001c000   00002000  00000000  00002000  RWIX
  MSMC3_DSP2_C66X       7001e000   00002000  00000000  00002000  RWIX
  MSMC3_DSP1_C7X        70020000   00002000  00000000  00002000  RWIX
  MSMC3_DSP2_C7X        70022000   00002000  00000000  00002000  RWIX
  MSMC3_MPU1_CPU0       70024000   00002000  00000000  00002000  RWIX
  MSMC3_MPU1_CPU1       70026000   00002000  00000000  00002000  RWIX
  MSMC3_MPU2_CPU0       70028000   00002000  00000000  00002000  RWIX
  MSMC3_MPU2_CPU1       7002a000   00002000  00000000  00002000  RWIX


SEGMENT ALLOCATION MAP

run origin  load origin   length   init length attrs members
----------  ----------- ---------- ----------- ----- -------
70014000    70014000    00000538   00000538    r-x
  70014000    70014000    00000400   00000400    r-x .text
  70014400    70014400    000000d0   000000d0    r-x .sbl_mcu_2_0_resetvector
  700144d0    700144d0    00000068   00000068    r-- .rodata


SECTION ALLOCATION MAP

 output                                  attributes/
section   page    origin      length       input sections
--------  ----  ----------  ----------   ----------------
.text      0    70014000    00000400     
                  70014000    00000294     sbl_multicore_r5.oer5f (.text)
                  70014294    000000f8     sbl_amp_multicore.oer5f (.text.SBLApp_main)
                  7001438c    00000074     --HOLE-- [fill = 0]

.sbl_mcu_2_0_resetvector 
*          0    70014400    000000d0     
                  70014400    000000ce     sbl_printf.oer5f (.sbl_mcu_2_0_resetvector)
                  700144ce    00000002     --HOLE-- [fill = 0]

.rodata    0    700144d0    00000068     
                  700144d0    00000022     sbl_amp_multicore.oer5f (.rodata.str1.35478256120839958921)
                  700144f2    0000001f     sbl_amp_multicore.oer5f (.rodata.str1.140578601370497022291)
                  70014511    00000011     sbl_printf.oer5f (.rodata.str1.29976943220859454841)
                  70014522    0000000a     sbl_amp_multicore.oer5f (.rodata.str1.178569032670608697161)
                  7001452c    00000007     sbl_amp_multicore.oer5f (.rodata.str1.152041185928364103251)
                  70014533    00000003     sbl_printf.oer5f (.rodata.str1.92065839560850382001)
                  70014536    00000002     --HOLE-- [fill = 0]

__llvm_prf_cnts 
*          0    70010000    00000000     UNINITIALIZED

__llvm_prf_bits 
*          0    70010000    00000000     UNINITIALIZED

.cinit     0    70010000    00000000     

    ******************************************************************************
            TI ARM Clang Linker Unix v3.2.2                    
******************************************************************************
>> Linked Thu Sep 18 13:41:02 2025

OUTPUT FILE NAME:   </home/gibbs/work/j721e/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/boot/sbl/example/k3MulticoreApp/binary/j721e/bootapp_boot_test_j721e_evm_mcu2_1TestApp_release.xer5f>
ENTRY POINT SYMBOL: "_sblTestResetVectors"  address: 70016000


MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
  MSMC3_MCU1_CPU0       70010000   00002000  00000000  00002000  RWIX
  MSMC3_MCU1_CPU1       70012000   00002000  00000000  00002000  RWIX
  MSMC3_MCU2_CPU0       70014000   00002000  00000000  00002000  RWIX
  MSMC3_MCU2_CPU1       70016000   00002000  000003f8  00001c08  RWIX
  MSMC3_MCU3_CPU0       70018000   00002000  00000000  00002000  RWIX
  MSMC3_MCU3_CPU1       7001a000   00002000  00000000  00002000  RWIX
  MSMC3_DSP1_C66X       7001c000   00002000  00000000  00002000  RWIX
  MSMC3_DSP2_C66X       7001e000   00002000  00000000  00002000  RWIX
  MSMC3_DSP1_C7X        70020000   00002000  00000000  00002000  RWIX
  MSMC3_DSP2_C7X        70022000   00002000  00000000  00002000  RWIX
  MSMC3_MPU1_CPU0       70024000   00002000  00000000  00002000  RWIX
  MSMC3_MPU1_CPU1       70026000   00002000  00000000  00002000  RWIX
  MSMC3_MPU2_CPU0       70028000   00002000  00000000  00002000  RWIX
  MSMC3_MPU2_CPU1       7002a000   00002000  00000000  00002000  RWIX


SEGMENT ALLOCATION MAP

run origin  load origin   length   init length attrs members
----------  ----------- ---------- ----------- ----- -------
70016000    70016000    000003f8   000003f8    r-x
  70016000    70016000    00000300   00000300    r-x .text
  70016300    70016300    000000d0   000000d0    r-x .sbl_mcu_2_1_resetvector
  700163d0    700163d0    00000028   00000028    r-- .rodata


SECTION ALLOCATION MAP

 output                                  attributes/
section   page    origin      length       input sections
--------  ----  ----------  ----------   ----------------
.text      0    70016000    00000300     
                  70016000    00000294     sbl_multicore_r5.oer5f (.text)
                  70016294    0000006c     sbl_amp_multicore.oer5f (.text.SBLApp_main)

.sbl_mcu_2_1_resetvector 
*          0    70016300    000000d0     
                  70016300    000000ce     sbl_printf.oer5f (.sbl_mcu_2_1_resetvector)
                  700163ce    00000002     --HOLE-- [fill = 0]

.rodata    0    700163d0    00000028     
                  700163d0    00000011     sbl_printf.oer5f (.rodata.str1.29976943220859454841)
                  700163e1    0000000a     sbl_amp_multicore.oer5f (.rodata.str1.178569032670608697161)
                  700163eb    00000007     sbl_amp_multicore.oer5f (.rodata.str1.152041185928364103251)
                  700163f2    00000003     sbl_printf.oer5f (.rodata.str1.92065839560850382001)
                  700163f5    00000003     --HOLE-- [fill = 0]

__llvm_prf_cnts 
*          0    70010000    00000000     UNINITIALIZED

__llvm_prf_bits 
*          0    70010000    00000000     UNINITIALIZED

.cinit     0    70010000    00000000     

MODULE SUMMARY

       Module                    code   ro data   rw data
       ------                    ----   -------   -------
    /home/gibbs/work/j721e/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/binary/bootapp_boot_test/obj/j721e/mcu2_1/release/
       sbl_multicore_r5.oer5f    660    0         0      
       sbl_printf.oer5f          206    20        0      
       sbl_amp_multicore.oer5f   108    17        0      
    +--+-------------------------+------+---------+---------+
       Total:                    974    37        0      
                                                         
    +--+-------------------------+------+---------+---------+
       Grand Total:              974    37        0      


GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name

    Do I miss understand anything?

    Thank You.

    Gibbs

  • 0 in reply to Gibbs Shih
    TI__Genius 16550 points

    Hi Gibbs,
    In your .map file for the GPIO Baremetal example, MCU2_0 and MCU2_1 share the same RESET_VECTORS address (0x41CE3000). In the original demo application, these addresses differ: MCU2_0 at (0x70014000) and MCU2_1 at (0x70016000). Did you observe the same lateapp1 hang issue when running both the original demo application and the GPIO Baremetal example?

    Regards,

    Karthik

  • 0 in reply to Karthikeyan S
    TI__Expert 6500 points

    Hi, Karthik

    Original demo link as below.

    It works for me, no app1 hangs.

    https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/10_00_00_05/exports/docs/pdk_jacinto_10_00_00_27/docs/userguide/jacinto/boot/boot_app.html

    but lateapp1 hangs only happen when I use combined App image for "GPIO_Baremetal_LedBlink_TestApp_mcu2_0_release.rprc" and "GPIO_Baremetal_LedBlink_TestApp_mcu2_1_release.rprc". this is different lateapp from original one.

    Should I change reset vector to 41ce3000?

    if the answer is yes, How to do it?

    Thank You.

    Gibbs

  • 0 in reply to Gibbs Shih
    TI__Genius 16550 points

    Hi Gibbs,
    Sorry, I’m a bit confused. Earlier, you mentioned booting Linux via MMCSD, but now you’re referring to booting lateapps via MMCSD. Could you please clarify your requirement and explain why you’re using lateapps?

    Regards,

    Karthik

  • 0 in reply to Karthikeyan S
    TI__Expert 6500 points

    Hi, Karthik

    Sorry late reply and confuse you.

    Lets me explain the back groud.

    * Background

    I try to test quick boot w/o SPL, so the only choice is boot w/ SBL from media MMCSD or OSPI flash. Because there are some hw issues in my OSPI flash on EVB, so I test MMCSD first. Because I think the idea should be very similar. Base on customer requirment, application should be "booting Linux w/ SBL which include multi-core images from MMCSD (or OSPI flash) " or "booting multi-core images only w/ SBL from MMCSD (or OSPI flash)". Both of them include lateapps.

    * Testing / Goal

    I test default example (binary) step by step, it works for me. But basically, customer may change (build) their own applcation (EX: R5 Core, lateapp1, lateapp2 ... etc), so I try to test how to combined our customerized own multi-core images and boot them success. This boot scenario include booting Linux w/ SBL which include multi-core images from MMCSD (or OSPI flash) " and "booting multi-core images only w/ SBL from MMCSD (or OSPI flash)".

    I found even SBL boot w/ HLOS or not in default example, both of them use the same lateapps.

    Sorry, This is my fist time try to test multi-core images booting.

    If I do some think wrong, pls correct me.

    Thank You.

    Gibbs

  • 0 in reply to Gibbs Shih
    TI__Genius 16550 points

    Hi Gibbs,

    I noticed that your two app binaries are mapped to the same memory region, which can cause the boot to fail when they’re combined. You can check the IPC ipc_echo_test_freertos example  it uses different memory ranges for each core (like MCU2_0_DDR_SPACE = 0xA2400000 and MCU2_1_DDR_SPACE = 0xA3400000). Try updating your linker files so each app uses its own non-overlapping address range.

    Screenshot from 2025-10-15 11-46-35.zip

    ipc_echo_test_freertos_map.zip

    Regards,

    Karthik