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Queries regarding EVM816x_Gerber_RevE

Kirti Makwana
Prodigy 20 points

Other Parts Discussed in Thread: TMS320DM8168

Hi,

I am working on a project in which I am using DDR3 Interface. I actually studied  Gerber for  EVM816x_Gerber_RevE. I have few queries regarding it as listed below.

 

  • AT length for clock in DDR3 is > 100 mils. Whereas in datasheet for tms320dm8168.pdf  it is defined to be within 100mils with a skew of 100mils. (what should be the length?)
  • A1+A2 length is greater than 3000 mils. Whereas it is defined to be within 2500 mils with a skew of 25 mils(what is maximum allowable length?) (Page no. 201 in tms320dm8168.pdf  )
  • Is there any relation between DQS and CLOCK signal for DDR3 as in case of DDR2?
  • You have defined range for CK and ADDR_CTRL group within CACLM-50 TO CACLM+50. Does that mean I can have clock and ADDR_CTRL signal should be within this range without having relation between ADDR_CTRL to CK.(I mean if CACLM is 2500 mils so I can set length for ADDR_CTRL and clock signal within the range of 2450 to 2550.)
  • Single ended trace impedance should be 50 ohm. What tolerance value is excepted.?
  • Differential  Trace impedance should be 100 ohm. What tolerance value is excepted.?
  • Width for DDR3 signal you  have defined is 4 mils. We normally set that value to 5 mils is it ok?
  • What should be the stackup for six layer board?
  • Values for placement of DDR3 should be as per Defined in Datasheet? How these values for x1, x2 and y1 are decided?  (given in tms320dm8168.pdf )
  • Is there any relation between DDR0 and DDR1 in terms of trace length for ADDR_CTRL, CK,DQs,DQ.?
  • Need information regarding placement of decoupling capacitors to stabilize Power plane.

Regards,

Kirti Makwana

  • 0
    TI__Intellectual 1610 points

    Most of the questions you are asked are addressed in the data sheet.  Please examine it more closely.  The governing specification is the device data sheet.  The EVM is an example of an implementation of the data sheet specification.   If there is a disagreement between the data sheet and EVM, the data sheet spec overrides.  It is expected that standard good high speed design practice is being followed in addition to the data sheet.

    • According to the data sheet, the AT length is specified as typical 500 mils, there is no explicit max.  See Table  8-24, Item 12.
    • Which net are you looking at?  I examined several address net A1+A2 segments in the EVM Allegro data base.  The etch length of the A1+A2 segements are ~2450 mils long, which is within the database spec.
    • Yes there is.  Staying withing all of the constraints of the PCB layout specification will ensure that any timing requirements, including CK to DQS, are met
    • This question/statement does not make sense.  If you are skew matching CK and ADDR_CTRL to the same spec, it has a relation by definition.   They are clearly not independent.
    • Datasheet, Table 8-18, Item 14.  +/- 5 ohms.  There is no explicit requirement that the board be 50 ohm nominal impedance.  There is a range that is allowed
    • The differential trace impedance should either be 2x the single ended impedance. 
    • There is no explicit requirement in the spec for nominal trace width.  You can literally set it to whatever you want.  All of specs dependent on the trace width are defined based on the trace width and thus scale to whatever w you pick.  Note, however, that w is controlled by your chosen PCB technology.  5 mil traces may not work for some BGA escapes.  This is a question that should be forwarded to your PCB layout house.  They should know how to set w appropriately.  4 mil is very common and recommended.
    • The stackup is flexible.  Table 8-17 shows a possible 6 layer stack.  The DDR layout spec does not specify an explicit stackup.  Any stackup is allowed that meets the requirements of Table 8-18 and allows you to meet the requirements of Section 8.3.2.6, Section 8.3.2.7, as well as the placement of the processor, DDR, and bypass capacitors.  There is an overall assumption of good high speed design practice.  Your PCB layout house should be able to suggest a good stackup.
    • X1, X2, and Y1 come from your board.  The data sheet simply specifies the maximums for these parameters in Table 8-19.  They are measured from the center of the device packages as shown in Figure 8-15.
    • The two DDR interfaces are independent, however they both must be laid out in accordance with the DDR layout spec in Section 8.3.2.
    • This information is provided in Table  8-21.  The bulk caps are in Table 8-20.  These tables cover the DDR interface bypass requirements.

    -Mike