C6Run : configuring part of L1cache as L1DSRAM

mike gp

Hello,

I am trying to run image processing algorithm on beagleboard XM Rev C using c6runapp.

For dsp, I want to use part of L1 cache as L1DSRAM to see variation in performance and tune the settings accordingly.

For example, I want to use 16KB of L1D cache and use remaining 16KB as L1DSRAM. This is in addition to already available 48KB of L1DSRAM.

So I should be able to use 64KB of L1DSRAM.

Can anyone explain me the procedure to do this for c6run application?

Thanks in advance.

over 13 years ago

0 Jeff L over 13 years ago

TI__Expert 5960 points

Hi Mike,

The caches on the Cortex-A8 are dedicated caches. There is no way to re-characterize the cache ram as typical SDRAM. However there is some ON-CHIP SDRAM (OCM-RAM).

By default only 2K is available, but it is possible to partition the RAM using the L3 firewall to 64K. Sorry but I'm not familiar with c6run.

0 mike gp over 13 years ago in reply to Jeff L

Intellectual 280 points

Hi Jeff,

I want to configure l1d cache on DSP side.

I have gone through few threads mentioned that it is possible to configure L1DCACHE as L1DSRAM for applications using codec engine.

But I want to know how to do this using C6RUN.

Thanks.

0 Jeff L over 13 years ago in reply to mike gp

TI__Expert 5960 points

Mike,

I misunderstood, I don't know much about the DSP cache. I thought the question was about the ARM processor. I will look into it. Hopefully in the mean time someone more knowledgeable will respond.

0 mike gp over 13 years ago in reply to Jeff L

Intellectual 280 points

Hi C6Run experts,

Can you please help me on this?

Regards,

Mike

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C6Run : configuring part of L1cache as L1DSRAM