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SK-AM62A-LP: DRAM Address Mapping

Maurice Lu
Prodigy 160 points

Part Number: SK-AM62A-LP

Tool/software:

Hi team,

We are using SK-AM62A-LP to validate our new DRAM product, but we met some problem.

When testing with stressapptest, it shows error as below:

    Error time: 6, Paddress:0x8c3f25309, Vaddress:0xf68ec308, read:0xfbfffffffbff7fff, reread:0xfbfffffffbff7fff, 3rdread:0xfbfffffffbff7fff, 4thread:0xfbfffffffbff7fff, 5thread:0xfbfffffffbff7fff, expected:0xfbfffffffbffffff

    Error time: 9, Paddress:0x8f3655dc5, Vaddress:0xf6576dc0, read:0x7fff7fffbfffffff, reread:0x7fff7fffbfffffff, 3rdread:0x7fff7fffbfffffff, 4thread:0x7fff7fffbfffffff, 5thread:0x7fff7fffbfffffff, expected:0x7fffffffbfffffff

Could you guide me about how do Paddress/Vaddress map to Column/Bank/Raw in DRAM?

Thanks.

Maurice

  • 0
    TI__Guru* 95381 points

    Hi Maurice,

    the Register Config tool defaults to the following mapping:  Row - CS- Bank - Column

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 160 points

    Hi James,

    Thanks for the reply.

    So if Paddress = 0x8c3f25309, then

    Raw = 8c3f

    CS = 2

    Bank = 5

    Column = 309

    Is that correct?

    Thanks.

  • +1 in reply to Maurice Lu
    TI__Guru* 95381 points

    Hi Maurice, not quite.  There 2 LSBs are part of the 32-bit word.  Also, the device DDR address memory map is  

    0x80000000 - 0xFFFFFFFF 2GByte

    0x880000000 - 0x8FFFFFFFF 2GByte

    0x900000000 - 0x97FFFFFFF 2GByte

    0x980000000 - 0x9FFFFFFFF 2GByte

    Note the address gap between the 1st and 2nd 2GByte region.  So the upper '0x8' is really just the 2nd 2GByte region, you wouldn't consider all of the four bits of 0x8 in the address map

    So the breakdown would be

    [1:0] Datapath

    [11:2] Column

    [14:12] Bank

    [15] CS

    [33:16] Row

    So for 0x8c3f25309, that would be

    Column = 00_1100_0010b

    Bank = 101b

    CS = 0b

    Row = 01_1100_0011_1111_0010 (Note the 01 in the MSB indicates the second 2GB region, which is indicated by 0x8 in the MSB of the address, as explained above)

    Hope this helps!

    Regards

    James

  • 0 in reply to JJD
    TI__Guru* 95381 points

    You may also want to simplify your testing by moving CS to the upper MSBs, this can be done by changing the following bit in the configuration file:

    -#define DDRSS_CTL_328_DATA 0x0B000001

    +#define DDRSS_CTL_328_DATA 0x0B000000  

    This will put rank 0 in the first two 2GByte regions (0x80000000-0xFFFFFFFF and 0x880000000-0x8FFFFFFFF), and rank 1 in the second two 2GB regions (0x90000000-0x9FFFFFFFF)

    Regards,

    Jams

  • 0 in reply to JJD
    Prodigy 160 points

    Hi James,

    Thanks for the reply.

    We have another Paddress, for example 0x8c3e5d149:

    What does [1:0] Datapath = 01b represent for?

    Also, we only use 1 Rank (CS0), but [15] CS = 1b.

    Shouldn't it be 0b? or did we miss something?

    Thanks.

    Maurice

  • 0 in reply to Maurice Lu
    TI__Guru* 95381 points

    Maurice, if you have just 1 rank, then i think you would ignore CS in the address map.  

    01b in datapath would be byte 1.  Since each access is 32bits (2 channels on AM62A), each access is 4 bytes, and the 2 LSBs would represent those bytes

    If you only are using one rank, then there is no interleaving with the CS, the physical address is linear.  From the processor point of view:

    0x080000000-0x0FFFFFFFF 1st 2Gbytes

    0x880000000-0x8FFFFFFFF 2nd 2Gbytes

    I'm assuming you are working with a 4GByte device?

    Regards,

    James

     

  • 0 in reply to JJD
    Prodigy 160 points

    Hi James,

    Thanks for the explanation, we'll discuss it internally first.

    Yes, we are working with a 4GB DRAM, x32, 1*Rank

    Meanwhile, I would like to ask AM62/AM64 DDR address mapping.

    For example, AM64 Paddress:0xa8edd241

    Are AM62/AM64 DDR address mapping same as AM62A?

    Thanks.

    Maurice

  • +1 in reply to Maurice Lu
    TI__Guru* 95381 points

    Hi Maurice, the mapping is the same, but the devices can support different capacities

    0x80000000 - 0xFFFFFFFF:  2GBytes all devices

    0x880000000 - 0x8FFFFFFFF: 2GBytes 

    0x900000000 - 0x97FFFFFFF: 2GBytes 

    0x980000000 - 0x9FFFFFFFF: 2GBytes 

    AM64 can only support 2GBytes for both LP4 and DDR4

    AM62 can support up to 2GByte LPDDR4 (single rank), 8GByte DDR4 (dual rank)

    AM62A/D/P can support up to 8GByte LPDDR4 (dual rank), DDR4 not supported

    Hope this helps!

    Regards,

    James

      

  • 0 in reply to JJD
    Prodigy 160 points

    Hi James,

    Many thanks for the clarification.

    Maurice